d01a995cd3
This patch feeds PsysPmax setting to FSP through UPD and adds a
psys_pmax member in chip information so that we can set PsysPmax
through DT. The PsysPmax needs to be set correctly mapping to maximum
system power. Otherwise, system performance would be limited due to
the default PsysPmax setting in FSP is only 21W.
BUG=None
BRANCH=None
TEST=Set psys_pmax to an example value eg 101 in DT && put debug code
in FSP to print the PsysPmax value before sending to Pcode, ensure
the setting is correctly programmed.
Change-Id: Ia88ea17bc661a388c5b9bc3e59abc27c9f262977
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/31505
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
366 lines
9.3 KiB
C
366 lines
9.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2008 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2017-2018 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _SOC_CHIP_H_
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#define _SOC_CHIP_H_
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#include <intelblocks/chip.h>
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#include <drivers/i2c/designware/dw_i2c.h>
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#include <intelblocks/gspi.h>
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#include <stdint.h>
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#include <soc/gpio.h>
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#include <soc/pch.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include <soc/pmc.h>
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#include <soc/serialio.h>
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#include <soc/usb.h>
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#include <soc/vr_config.h>
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#if IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H)
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#include <soc/gpio_defs_cnp_h.h>
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#else
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#include <soc/gpio_defs.h>
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#endif
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struct soc_intel_cannonlake_config {
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/* Common struct containing soc config data required by common code */
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struct soc_intel_common_config common_soc_config;
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/* GPE configuration */
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uint32_t gpe0_en_1; /* GPE0_EN_31_0 */
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uint32_t gpe0_en_2; /* GPE0_EN_63_32 */
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uint32_t gpe0_en_3; /* GPE0_EN_95_64 */
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uint32_t gpe0_en_4; /* GPE0_EN_127_96 / GPE_STD */
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/* Gpio group routed to each dword of the GPE0 block. Values are
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* of the form GPP_[A:G] or GPD. */
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uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */
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uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */
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uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */
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/* Generic IO decode ranges */
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uint32_t gen1_dec;
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uint32_t gen2_dec;
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uint32_t gen3_dec;
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uint32_t gen4_dec;
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/* Enable S0iX support */
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int s0ix_enable;
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/* Enable DPTF support */
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int dptf_enable;
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/* Deep SX enable for both AC and DC */
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int deep_s3_enable_ac;
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int deep_s3_enable_dc;
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int deep_s5_enable_ac;
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int deep_s5_enable_dc;
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/* Deep Sx Configuration
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* DSX_EN_WAKE_PIN - Enable WAKE# pin
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* DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin
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* DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin */
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uint32_t deep_sx_config;
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/* TCC activation offset */
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uint32_t tcc_offset;
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uint64_t PlatformMemorySize;
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uint8_t SmramMask;
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uint8_t MrcFastBoot;
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uint32_t TsegSize;
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uint16_t MmioSize;
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/* DDR Frequency Limit. Maximum Memory Frequency Selections in Mhz.
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* Options : 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933, 0(Auto) */
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uint16_t DdrFreqLimit;
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/* SAGV Low Frequency Selections in Mhz.
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* Options : 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933, 0(Auto) */
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uint16_t FreqSaGvLow;
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/* SAGV Mid Frequency Selections in Mhz.
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* Options : 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933, 0(Auto) */
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uint16_t FreqSaGvMid;
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/* System Agent dynamic frequency support. Only effects ULX/ULT CPUs.
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* For CNL, options are as following
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* When enabled, memory will be training at three different frequencies.
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* 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled
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* For WHL/CFL options are as following
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* When enabled, memory will be training at two different frequencies.
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* 0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled*/
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enum {
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SaGv_Disabled,
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SaGv_FixedLow,
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#if !IS_ENABLED(CONFIG_SOC_INTEL_COMMON_CANNONLAKE_BASE)
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SaGv_FixedMid,
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#endif
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SaGv_FixedHigh,
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SaGv_Enabled,
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} SaGv;
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/* Rank Margin Tool. 1:Enable, 0:Disable */
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uint8_t RMT;
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/* USB related */
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struct usb2_port_config usb2_ports[16];
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struct usb3_port_config usb3_ports[10];
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uint8_t SsicPortEnable;
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/* Wake Enable Bitmap for USB2 ports */
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uint16_t usb2_wake_enable_bitmap;
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/* Wake Enable Bitmap for USB3 ports */
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uint16_t usb3_wake_enable_bitmap;
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/* SATA related */
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enum {
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Sata_AHCI,
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Sata_RAID,
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} SataMode;
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uint8_t SataSalpSupport;
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uint8_t SataPortsEnable[8];
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uint8_t SataPortsDevSlp[8];
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/* Audio related */
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uint8_t PchHdaDspEnable;
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/* Enable/Disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1 */
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uint8_t PchHdaAudioLinkHda;
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uint8_t PchHdaAudioLinkDmic0;
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uint8_t PchHdaAudioLinkDmic1;
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uint8_t PchHdaAudioLinkSsp0;
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uint8_t PchHdaAudioLinkSsp1;
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uint8_t PchHdaAudioLinkSsp2;
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uint8_t PchHdaAudioLinkSndw1;
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uint8_t PchHdaAudioLinkSndw2;
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uint8_t PchHdaAudioLinkSndw3;
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uint8_t PchHdaAudioLinkSndw4;
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/* PCIe Root Ports */
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uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
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/* PCIe output clocks type to Pcie devices.
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* 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
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* 0xFF: not used */
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uint8_t PcieClkSrcUsage[CONFIG_MAX_ROOT_PORTS];
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/* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to
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* clksrc. */
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uint8_t PcieClkSrcClkReq[CONFIG_MAX_ROOT_PORTS];
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/* PCIe LTR(Latency Tolerance Reporting) mechanism */
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uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
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/* eMMC and SD */
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uint8_t ScsEmmcHs400Enabled;
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/* Need to update DLL setting to get Emmc running at HS400 speed */
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uint8_t EmmcHs400DllNeed;
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/* 0-39: number of active delay for RX strobe, unit is 125 psec */
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uint8_t EmmcHs400RxStrobeDll1;
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/* 0-78: number of active delay for TX data, unit is 125 psec */
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uint8_t EmmcHs400TxDataDll;
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/* Integrated Sensor */
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uint8_t PchIshEnable;
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/* Heci related */
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uint8_t Heci3Enabled;
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/* Gfx related */
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uint8_t IgdDvmt50PreAlloc;
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uint8_t InternalGfx;
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uint8_t SkipExtGfxScan;
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uint32_t GraphicsConfigPtr;
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uint8_t Device4Enable;
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/* GPIO IRQ Select. The valid value is 14 or 15 */
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uint8_t GpioIrqRoute;
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/* SCI IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23 */
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uint8_t SciIrqSelect;
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/* TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23 */
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uint8_t TcoIrqSelect;
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uint8_t TcoIrqEnable;
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/* VrConfig Settings for 5 domains
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* 0 = System Agent, 1 = IA Core, 2 = Ring,
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* 3 = GT unsliced, 4 = GT sliced */
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struct vr_config domain_vr_config[NUM_VR_DOMAINS];
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/* HeciEnabled decides the state of Heci1 at end of boot
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* Setting to 0 (default) disables Heci1 and hides the device from OS */
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uint8_t HeciEnabled;
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/* PL1 Override value in Watts */
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uint32_t tdp_pl1_override;
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/* PL2 Override value in Watts */
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uint32_t tdp_pl2_override;
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/* SysPL2 Value in Watts */
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uint32_t tdp_psyspl2;
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/* SysPL3 Value in Watts */
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uint32_t tdp_psyspl3;
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/* SysPL3 window size */
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uint32_t tdp_psyspl3_time;
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/* SysPL3 duty cycle */
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uint32_t tdp_psyspl3_dutycycle;
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/* PL4 Value in Watts */
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uint32_t tdp_pl4;
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/* Estimated maximum platform power in Watts */
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uint16_t psys_pmax;
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/* Intel Speed Shift Technology */
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uint8_t speed_shift_enable;
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/* Enable VR specific mailbox command
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* 00b - no VR specific cmd sent
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* 01b - VR mailbox cmd specifically for the MPS IMPV8 VR will be sent
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* 10b - VR specific cmd sent for PS4 exit issue
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* 11b - Reserved */
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uint8_t SendVrMbxCmd;
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/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
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uint8_t eist_enable;
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/* Statically clock gate 8254 PIT. */
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uint8_t clock_gate_8254;
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/* Enable C6 DRAM */
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uint8_t enable_c6dram;
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/*
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* PRMRR size setting with below options
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* 0x00100000 - 1MiB
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* 0x02000000 - 32MiB and beyond
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*/
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uint32_t PrmrrSize;
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uint8_t PmTimerDisabled;
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/*
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* SLP_S3 Minimum Assertion Width Policy
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* 1 = 60us
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* 2 = 1ms (default)
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* 3 = 50ms
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* 4 = 2s
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*/
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uint8_t PchPmSlpS3MinAssert;
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/*
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* SLP_S4 Minimum Assertion Width Policy
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* 1 = 1s
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* 2 = 2s
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* 3 = 3s
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* 4 = 4s (default)
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*/
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uint8_t PchPmSlpS4MinAssert;
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/*
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* SLP_SUS Minimum Assertion Width Policy
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* 1 = 0ms
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* 2 = 500ms
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* 3 = 1s (default)
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* 4 = 4s
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*/
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uint8_t PchPmSlpSusMinAssert;
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/*
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* SLP_A Minimum Assertion Width Policy
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* 1 = 0ms
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* 2 = 4s
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* 3 = 98ms (default)
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* 4 = 2s
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*/
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uint8_t PchPmSlpAMinAssert;
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/* Desired platform debug type. */
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enum {
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DebugConsent_Disabled,
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DebugConsent_DCI_DBC,
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DebugConsent_DCI,
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DebugConsent_USB3_DBC,
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DebugConsent_XDP, /* XDP/Mipi60 */
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DebugConsent_USB2_DBC,
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} DebugConsent;
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/*
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* SerialIO device mode selection:
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*
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* Device index:
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* PchSerialIoIndexI2C0
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* PchSerialIoIndexI2C1
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* PchSerialIoIndexI2C2
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* PchSerialIoIndexI2C3
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* PchSerialIoIndexI2C4
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* PchSerialIoIndexI2C5
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* PchSerialIoIndexSPI0
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* PchSerialIoIndexSPI1
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* PchSerialIoIndexSPI2
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* PchSerialIoIndexUART0
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* PchSerialIoIndexUART1
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* PchSerialIoIndexUART2
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*
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* Mode select:
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* PchSerialIoDisabled
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* PchSerialIoPci
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* PchSerialIoAcpi
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* PchSerialIoHidden
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*/
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uint8_t SerialIoDevMode[PchSerialIoIndexMAX];
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/* GPIO SD card detect pin */
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unsigned int sdcard_cd_gpio;
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/* Enable Pch iSCLK */
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uint8_t pch_isclk;
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/* Intel VT configuration */
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uint8_t VtdDisable;
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uint8_t VmxEnable;
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/*
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* Acoustic Noise Mitigation
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* 0b - Disable
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* 1b - Enable noise mitigation
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*/
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uint8_t AcousticNoiseMitigation;
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/*
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* Disable Fast Package C-state ramping
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* Need to set AcousticNoiseMitigation = '1' first
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* 0b - Enabled
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* 1b - Disabled
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*/
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uint8_t FastPkgCRampDisableIa;
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uint8_t FastPkgCRampDisableGt;
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uint8_t FastPkgCRampDisableSa;
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uint8_t FastPkgCRampDisableFivr;
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/*
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* Adjust the VR slew rates
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* Need to set AcousticNoiseMitigation = '1' first
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* 000b - Fast/2
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* 001b - Fast/4
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* 010b - Fast/8
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* 011b - Fast/16
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*/
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uint8_t SlowSlewRateForIa;
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uint8_t SlowSlewRateForGt;
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uint8_t SlowSlewRateForSa;
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uint8_t SlowSlewRateForFivr;
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/* DMI Power Optimizer */
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uint8_t dmipwroptimize;
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/* SATA Power Optimizer */
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uint8_t satapwroptimize;
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};
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typedef struct soc_intel_cannonlake_config config_t;
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#endif
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