3d299c4b09
The management engine is slow, requiring at least 500ms between when the Dram Init Done message is sent (right after memory training) to when the MBP will report that it is successfully cleared and that the ME can finally be sent the EOP message. Currently this is adding 100-150ms to the boot time. If we defer waiting for the MBP Clear indicator until the finalize step we can gain back that lost time. boot on falco with SMI debugging enabled to ensure that the ME is locked down in the finalize step: Finalizing Coreboot SMI# #0 SMI_STS: PM1 APM ME: MBP cleared ME: mkhi_end_of_post ME: END OF POST message successful (0) Change-Id: Icab4c8c8e00eea67bed5e8154d91a1eb48a492d1 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/62633 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4375 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
71 lines
1.9 KiB
C
71 lines
1.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <console/post_codes.h>
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#include <spi-generic.h>
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#include "me.h"
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#include "pch.h"
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void intel_pch_finalize_smm(void)
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{
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/* Lock down Management Engine */
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intel_me_finalize_smm();
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/* Set SPI opcode menu */
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RCBA16(0x3894) = SPI_OPPREFIX;
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RCBA16(0x3896) = SPI_OPTYPE;
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RCBA32(0x3898) = SPI_OPMENU_LOWER;
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RCBA32(0x389c) = SPI_OPMENU_UPPER;
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/* Lock SPIBAR */
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RCBA32_OR(0x3804, (1 << 15));
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#if CONFIG_SPI_FLASH_SMM
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/* Re-init SPI driver to handle locked BAR */
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spi_init();
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#endif
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/* TCLOCKDN: TC Lockdown */
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RCBA32_OR(0x0050, (1 << 31));
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/* BIOS Interface Lockdown */
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RCBA32_OR(0x3410, (1 << 0));
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/* Function Disable SUS Well Lockdown */
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RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7));
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/* Global SMI Lock */
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pci_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4);
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/* GEN_PMCON Lock */
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pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2));
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/* PMSYNC */
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RCBA32_OR(PMSYNC_CONFIG, (1 << 31));
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/* R/WO registers */
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RCBA32(0x21a4) = RCBA32(0x21a4);
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pci_write_config32(PCI_DEV(0, 27, 0), 0x74,
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pci_read_config32(PCI_DEV(0, 27, 0), 0x74));
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/* Indicate finalize step with post code */
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outb(POST_OS_BOOT, 0x80);
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}
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