a73b93157f
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
73 lines
2.1 KiB
C
73 lines
2.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <reg_script.h>
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#include <soc/iosf.h>
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#include <soc/nvs.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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#include "chip.h"
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static const struct reg_script emmc_ops[] = {
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/* Enable 2ms card stable feature. */
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REG_PCI_OR32(0xa8, (1 << 24)),
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/* Enable HS200 */
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REG_PCI_WRITE32(0xa0, 0x446cc801),
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REG_PCI_WRITE32(0xa4, 0x80000807),
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/* cfio_regs_score_special_bits.sdio1_dummy_loopback_en=1 */
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REG_IOSF_OR(IOSF_PORT_SCORE, 0x49c0, (1 << 3)),
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/* CLKGATE_EN_1 . cr_scc_mipihsi_clkgate_en = 1 */
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REG_IOSF_RMW(IOSF_PORT_CCU, 0x1c, ~(3 << 26), (1 << 26)),
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/* Set slew for HS200 */
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REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c0, ~0x3c, 0x3c),
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REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c4, ~0x3c, 0x3c),
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/* Max timeout */
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REG_RES_WRITE8(PCI_BASE_ADDRESS_0, 0x002e, 0x0e),
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REG_SCRIPT_END,
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};
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static void emmc_init(device_t dev)
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{
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struct soc_intel_baytrail_config *config = dev->chip_info;
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printk(BIOS_DEBUG, "eMMC init\n");
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reg_script_run_on_dev(dev, emmc_ops);
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if (config->scc_acpi_mode)
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scc_enable_acpi_mode(dev, SCC_MMC_CTL, SCC_NVS_MMC);
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}
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static struct device_operations device_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = emmc_init,
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.enable = NULL,
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.scan_bus = NULL,
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.ops_pci = &soc_pci_ops,
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};
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static const struct pci_driver southcluster __pci_driver = {
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.ops = &device_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = MMC_DEVID,
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};
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