d129d43ea7
Use of device_t has been abandoned in ramstage. Change-Id: I8e549e4222ae2ed6b9c46f81c5b5253e8b227ee8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
131 lines
3.3 KiB
C
131 lines
3.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <boardid.h>
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#include <boot/coreboot_tables.h>
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#include <delay.h>
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#include <device/device.h>
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#include <gpio.h>
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#include <soc/clock.h>
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#include <soc/soc_services.h>
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#include <soc/usb.h>
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#include <symbols.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include "mmu.h"
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#define USB_ENABLE_GPIO 51
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static void setup_usb(void)
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{
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#if !IS_ENABLED(CONFIG_BOARD_VARIANT_AP148)
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gpio_tlmm_config_set(USB_ENABLE_GPIO, FUNC_SEL_GPIO,
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GPIO_PULL_UP, GPIO_10MA, GPIO_ENABLE);
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gpio_set(USB_ENABLE_GPIO, 1);
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#endif
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usb_clock_config();
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setup_usb_host1();
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}
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#define TPM_RESET_GPIO 22
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static void setup_tpm(void)
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{
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if (board_id() != BOARD_ID_PROTO_0)
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return; /* Only proto0 have TPM reset connected to GPIO22 */
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gpio_tlmm_config_set(TPM_RESET_GPIO, FUNC_SEL_GPIO, GPIO_PULL_UP,
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GPIO_4MA, GPIO_ENABLE);
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/*
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* Generate a reset pulse. The spec calls for 80 us minimum, let's
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* make it twice as long. If the output was driven low originally, the
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* reset pulse will be even longer.
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*/
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gpio_set(TPM_RESET_GPIO, 0);
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udelay(160);
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gpio_set(TPM_RESET_GPIO, 1);
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}
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#define SW_RESET_GPIO 26
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static void assert_sw_reset(void)
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{
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if (board_id() == BOARD_ID_PROTO_0)
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return;
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/*
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* only proto0.2 and later care about this. We want to keep the
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* ethernet switch in reset, otherwise it comes up in default
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* (bridging) mode.
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*/
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gpio_tlmm_config_set(SW_RESET_GPIO, FUNC_SEL_GPIO,
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GPIO_PULL_UP, GPIO_4MA, GPIO_ENABLE);
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gpio_set(SW_RESET_GPIO, 1);
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}
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static void mainboard_init(struct device *dev)
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{
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/* disable mmu and d-cache before setting up secure world.*/
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dcache_mmu_disable();
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start_tzbsp();
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/* Setup mmu and d-cache again as non secure entries. */
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setup_mmu(DRAM_INITIALIZED);
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start_rpm();
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setup_usb();
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assert_sw_reset();
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setup_tpm();
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/* Functionally a 0-cost no-op if NAND is not present */
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board_nand_init();
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#if IS_ENABLED(CONFIG_CHROMEOS)
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/* Copy WIFI calibration data into CBMEM. */
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cbmem_add_vpd_calibration_data();
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#endif
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/*
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* Make sure bootloader can issue sounds The frequency is calculated
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* as "<frame_rate> * <bit_width> * <channels> * 4", i.e.
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*
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* 48000 * 2 * 16 * 4 = 6144000
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*/
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audio_clock_config(6144000);
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}
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static void mainboard_enable(struct device *dev)
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{
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dev->ops->init = &mainboard_init;
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}
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struct chip_operations mainboard_ops = {
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.name = "storm",
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.enable_dev = mainboard_enable,
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};
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void lb_board(struct lb_header *header)
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{
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struct lb_range *dma;
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dma = (struct lb_range *)lb_new_record(header);
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dma->tag = LB_TAB_DMA;
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dma->size = sizeof(*dma);
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dma->range_start = (uintptr_t)_dma_coherent;
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dma->range_size = _dma_coherent_size;
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#if IS_ENABLED(CONFIG_CHROMEOS)
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/* Retrieve the switch interface MAC addresses. */
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lb_table_add_macs_from_vpd(header);
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#endif
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}
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