6481cfb15d
Historically we had set panel timing in the mainboard gma code. This goes back to the replay-attack video startup. We can let the haswell gma code set these values from the device tree settings. Change-Id: If32150d2857241ca2d2c88880086f49d25815d76 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://chromium-review.googlesource.com/180521 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit 406eab3ca6a9bc59382866817786bf96bbb19d56) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6911 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
251 lines
8 KiB
C
251 lines
8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <types.h>
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#include <string.h>
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#include <stdlib.h>
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#include <device/device.h>
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#include <device/device.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <console/console.h>
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#include <delay.h>
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#include <pc80/mc146818rtc.h>
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#include <arch/acpi.h>
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#include <arch/io.h>
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#include <arch/interrupt.h>
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#include <boot/coreboot_tables.h>
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#include <smbios.h>
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#include <device/pci.h>
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#include <ec/google/chromeec/ec.h>
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#include <cbfs_core.h>
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#include <cpu/x86/tsc.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/msr.h>
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#include <edid.h>
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#include <drivers/intel/gma/i915.h>
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#include <northbridge/intel/haswell/haswell.h>
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#include "mainboard.h"
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/*
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* Here is the rough outline of how we bring up the display:
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* 1. Upon power-on Sink generates a hot plug detection pulse thru HPD
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* 2. Source determines video mode by reading DPCD receiver capability field
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* (DPCD 00000h to 0000Dh) including eDP CP capability register (DPCD
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* 0000Dh).
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* 3. Sink replies DPCD receiver capability field.
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* 4. Source starts EDID read thru I2C-over-AUX.
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* 5. Sink replies EDID thru I2C-over-AUX.
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* 6. Source determines link configuration, such as MAX_LINK_RATE and
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* MAX_LANE_COUNT. Source also determines which type of eDP Authentication
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* method to use and writes DPCD link configuration field (DPCD 00100h to
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* 0010Ah) including eDP configuration set (DPCD 0010Ah).
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* 7. Source starts link training. Sink does clock recovery and equalization.
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* 8. Source reads DPCD link status field (DPCD 00200h to 0020Bh).
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* 9. Sink replies DPCD link status field. If main link is not stable, Source
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* repeats Step 7.
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* 10. Source sends MSA (Main Stream Attribute) data. Sink extracts video
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* parameters and recovers stream clock.
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* 11. Source sends video data.
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*/
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/* how many bytes do we need for the framebuffer?
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* Well, this gets messy. To get an exact answer, we have
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* to ask the panel, but we'd rather zero the memory
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* and set up the gtt while the panel powers up. So,
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* we take a reasonable guess, secure in the knowledge that the
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* MRC has to overestimate the number of bytes used.
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* 8 MiB is a very safe guess. There may be a better way later, but
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* fact is, the initial framebuffer is only very temporary. And taking
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* a little long is ok; this is done much faster than the AUX
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* channel is ready for IO.
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*/
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#define FRAME_BUFFER_BYTES (8*MiB)
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/* how many 4096-byte pages do we need for the framebuffer?
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* There are hard ways to get this, and easy ways:
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* there are FRAME_BUFFER_BYTES/4096 pages, since pages are 4096
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* on this chip (and in fact every Intel graphics chip we've seen).
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*/
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#define FRAME_BUFFER_PAGES (FRAME_BUFFER_BYTES/(4096))
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static int i915_init_done = 0;
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/* fill the palette. */
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static void palette(void)
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{
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int i;
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unsigned long color = 0;
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for(i = 0; i < 256; i++, color += 0x010101){
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gtt_write(_LGC_PALETTE_A + (i<<2),color);
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}
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}
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void mainboard_train_link(struct intel_dp *intel_dp)
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{
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u8 read_val;
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u8 link_status[DP_LINK_STATUS_SIZE];
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gtt_write(DP_TP_CTL(intel_dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE);
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gtt_write(DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH |0x80000011);
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intel_dp_get_training_pattern(intel_dp, &read_val);
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intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_1 | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
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intel_dp_get_lane_count(intel_dp, &read_val);
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intel_dp_set_training_lane0(intel_dp, DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0);
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intel_dp_get_link_status(intel_dp, link_status);
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gtt_write(DP_TP_CTL(intel_dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT2);
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intel_dp_get_training_pattern(intel_dp, &read_val);
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intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_2 | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
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intel_dp_get_link_status(intel_dp, link_status);
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intel_dp_get_lane_align_status(intel_dp, &read_val);
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intel_dp_get_training_pattern(intel_dp, &read_val);
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intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_DISABLE | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
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}
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#define TEST_GFX 0
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#if TEST_GFX
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static void test_gfx(struct intel_dp *dp)
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{
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int i;
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/* This is a sanity test code which fills the screen with two bands --
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green and blue. It is very useful to ensure all the initializations
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are made right. Thus, to be used only for testing, not otherwise
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*/
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for (i = 0; i < (dp->edid.va - 4); i++) {
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u32 *l;
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int j;
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u32 tcolor = 0x0ff;
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for (j = 0; j < (dp->edid.ha-4); j++) {
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if (j == (dp->edid.ha/2)) {
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tcolor = 0xff00;
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}
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l = (u32*)(graphics + i * dp->stride + j * sizeof(tcolor));
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memcpy(l,&tcolor,sizeof(tcolor));
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}
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}
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}
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#else
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static void test_gfx(struct intel_dp *dp) {}
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#endif
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void mainboard_set_port_clk_dp(struct intel_dp *intel_dp)
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{
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u32 ddi_pll_sel = 0;
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switch (intel_dp->link_bw) {
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case DP_LINK_BW_1_62:
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ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
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break;
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case DP_LINK_BW_2_7:
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ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
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break;
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case DP_LINK_BW_5_4:
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ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
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break;
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default:
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printk(BIOS_ERR, "invalid link bw %d\n", intel_dp->link_bw);
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return;
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}
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gtt_write(PORT_CLK_SEL(intel_dp->port), ddi_pll_sel);
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}
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int panel_lightup(struct intel_dp *dp, unsigned int init_fb)
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{
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int i;
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int edid_ok;
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int pixels = FRAME_BUFFER_BYTES/64;
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void runio(struct intel_dp *dp);
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dp->gen = 8; // This is gen 8 which we believe is Haswell
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dp->is_haswell = 1;
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dp->DP = 0x2;
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/* These values are used for training the link */
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dp->lane_count = 2;
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dp->link_bw = DP_LINK_BW_2_7;
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dp->pipe = PIPE_A;
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dp->port = PORT_A;
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dp->plane = PLANE_A;
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dp->clock = 160000;
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dp->pipe_bits_per_pixel = 32;
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dp->type = INTEL_OUTPUT_EDP;
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dp->output_reg = DP_A;
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/* observed from YABEL. */
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dp->aux_clock_divider = 0xe1;
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dp->precharge = 3;
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/* 1. Normal mode: Set the first page to zero and make
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all GTT entries point to the same page
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2. Developer/Recovery mode: We do not zero out all
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the pages pointed to by GTT in order to avoid wasting time */
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if (init_fb){
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set_translation_table(0, FRAME_BUFFER_PAGES, dp->physbase, 4096);
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memset((void *)dp->graphics, 0x55, FRAME_BUFFER_PAGES*4096);
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} else {
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set_translation_table(0, FRAME_BUFFER_PAGES, dp->physbase, 0);
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memset((void*)dp->graphics, 0, 4096);
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}
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dp->address = 0x50;
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if ( !intel_dp_get_dpcd(dp) )
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goto fail;
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intel_dp_i2c_aux_ch(dp, MODE_I2C_WRITE, 0, NULL);
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for(dp->edidlen = i = 0; i < sizeof(dp->rawedid); i++){
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if (intel_dp_i2c_aux_ch(dp, MODE_I2C_READ,
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0x50, &dp->rawedid[i]) < 0)
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break;
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dp->edidlen++;
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}
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edid_ok = decode_edid(dp->rawedid, dp->edidlen, &dp->edid);
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printk(BIOS_SPEW, "decode edid returns %d\n", edid_ok);
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compute_display_params(dp);
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intel_ddi_set_pipe_settings(dp);
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runio(dp);
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palette();
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pixels = dp->edid.ha * (dp->edid.va-4) * 4;
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printk(BIOS_SPEW, "ha=%d, va=%d\n",dp->edid.ha, dp->edid.va);
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test_gfx(dp);
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set_vbe_mode_info_valid(&dp->edid, (uintptr_t)dp->graphics);
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i915_init_done = 1;
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return i915_init_done;
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fail:
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printk(BIOS_SPEW, "Graphics could not be started;");
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printk(BIOS_SPEW, "Returning.\n");
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return 0;
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}
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