1f088c8757
Enable VBOOT support on all devices that have a 12 MiB flash, using RW_MAIN_A + RW_MAIN_B partition, allowing the use of tianocore payload in both RW_MAIN_A, RW_MAIN_B and WP_RO. * Add VBNV section to cmos.layout * Add FMAP for VBOOT * Select Kconfigs for VBOOT * Enable VBOOT_SLOTS_RW_AB by default The VBNV is intentionally not covered by the CMOS checksum. Tested on x230 and T440p. Change-Id: I8a35a06ece1e9d57a2ef23970e61ae26fafce543 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Jonas Moehle <ad-min@mailbox.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
34 lines
612 B
Text
34 lines
612 B
Text
FLASH@0xff400000 0xc00000 {
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SI_ALL@0x0 0x500000 {
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SI_DESC@0x0 0x1000
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SI_GBE@0x1000 0x2000
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SI_ME
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}
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SI_BIOS@0x500000 0x700000 {
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RW_SECTION_A 0x280000 {
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VBLOCK_A 0x10000
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FW_MAIN_A(CBFS)
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RW_FWID_A 0x40
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}
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RW_SECTION_B 0x280000 {
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VBLOCK_B 0x10000
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FW_MAIN_B(CBFS)
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RW_FWID_B 0x40
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}
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UNIFIED_MRC_CACHE@0x500000 0x20000 {
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RECOVERY_MRC_CACHE@0x0 0x10000
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RW_MRC_CACHE@0x10000 0x10000
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}
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RW_VPD(PRESERVE) 0x1000
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SMMSTORE(PRESERVE)@0x521000 0x40000
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WP_RO {
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FMAP 0x800
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RO_FRID 0x40
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RO_PADDING 0x7c0
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RO_VPD(PRESERVE) 0x1000
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GBB 0x1e000
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COREBOOT(CBFS)
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}
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}
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}
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