01b3c40bfe
Move disabling of PM Timer to SoC PMC code. The original reason for placing that in `finalize` [1] was FSP hanging due to use of the PM timer without enabling timer emulation first in coreboot, which was added later [2]. [1] commit6c1bf27dae(intel/skylake: disable ACPI PM Timer to enable XTAL OSC shutdown) [2] commitf004f66ca7(soc/intel/skylake: Enable ACPI PM timer emulation on all CPUs) Change-Id: I354c3aea0c8c1f8ff3d698e0636932b7b76125f7 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
74 lines
1.6 KiB
C
74 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
|
|
|
|
/*
|
|
* This file is created based on Intel Tiger Lake Processor PCH Datasheet
|
|
* Document number: 575857
|
|
* Chapter number: 4, 29
|
|
*/
|
|
|
|
#include <bootstate.h>
|
|
#include <commonlib/console/post_codes.h>
|
|
#include <console/console.h>
|
|
#include <cpu/x86/smm.h>
|
|
#include <device/mmio.h>
|
|
#include <device/pci.h>
|
|
#include <intelblocks/lpc_lib.h>
|
|
#include <intelblocks/pcr.h>
|
|
#include <intelblocks/pmclib.h>
|
|
#include <intelblocks/systemagent.h>
|
|
#include <intelblocks/tco.h>
|
|
#include <intelblocks/thermal.h>
|
|
#include <intelpch/lockdown.h>
|
|
#include <soc/p2sb.h>
|
|
#include <soc/pci_devs.h>
|
|
#include <soc/pcr_ids.h>
|
|
#include <soc/pm.h>
|
|
#include <soc/smbus.h>
|
|
#include <soc/soc_chip.h>
|
|
#include <soc/systemagent.h>
|
|
#include <spi-generic.h>
|
|
|
|
static void pch_finalize(void)
|
|
{
|
|
/* TCO Lock down */
|
|
tco_lockdown();
|
|
|
|
/* TODO: Add Thermal Configuration */
|
|
|
|
pmc_clear_pmcon_sts();
|
|
}
|
|
|
|
static void tbt_finalize(void)
|
|
{
|
|
int i;
|
|
const struct device *dev;
|
|
|
|
/* Disable Thunderbolt PCIe root ports bus master */
|
|
for (i = 0; i < NUM_TBT_FUNCTIONS; i++) {
|
|
dev = pcidev_path_on_root(SA_DEVFN_TBT(i));
|
|
if (dev)
|
|
pci_dev_disable_bus_master(dev);
|
|
}
|
|
}
|
|
|
|
static void sa_finalize(void)
|
|
{
|
|
if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT)
|
|
sa_lock_pam();
|
|
}
|
|
|
|
static void soc_finalize(void *unused)
|
|
{
|
|
printk(BIOS_DEBUG, "Finalizing chipset.\n");
|
|
|
|
pch_finalize();
|
|
apm_control(APM_CNT_FINALIZE);
|
|
tbt_finalize();
|
|
sa_finalize();
|
|
|
|
/* Indicate finalize step with post code */
|
|
post_code(POST_OS_BOOT);
|
|
}
|
|
|
|
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
|
|
BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL);
|