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Subrata Banik d2cadc39f3 soc/intel/cannonlake: Refactor memory layout calculation 
This patch split entire memory layout calculation into
two parts. 1. Generic memory layout 2. SoC specific
reserve memory layout.

usable memory start = TOLUD - Generic memory size -
                   - soc specific reserve memory size.

Change-Id: I56e253504a331c0663efb2b90eaa0567613aa508
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 		2017-10-18 01:10:41 +00:00
..
acpi
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arch arch/x86: initialize EBDA in S3 and S0/S5 path 2017-10-16 16:56:19 +00:00
commonlib
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console
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cpu cpu/amd: Fix spelling of *implementation* 2017-10-16 02:05:16 +00:00
device src/device: Update LTR configuration scheme 2017-10-13 15:21:48 +00:00
drivers drivers/elog: Fix debug build errors 2017-10-16 16:10:51 +00:00
ec google/chromeec: Drain all MKBP events while clearing host events 2017-10-18 00:38:49 +00:00
include src/device: Update LTR configuration scheme 2017-10-13 15:21:48 +00:00
lib drivers/elog: Fix debug build errors 2017-10-16 16:10:51 +00:00
mainboard intel/cannonlake_rvp: enable HS400 2017-10-17 22:49:43 +00:00
northbridge sandybridge/acpi: remove unnessary check of PCI IDs 2017-10-16 20:24:44 +00:00
soc soc/intel/cannonlake: Refactor memory layout calculation 2017-10-18 01:10:41 +00:00
southbridge sb/amd/sb700/lpc.c: Optimize code flow for less indentation 2017-10-12 08:08:22 +00:00
superio
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vboot vboot: Exclude platform specific files from RW cbfs 2017-10-12 18:33:42 +00:00
vendorcode
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Kconfig
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