c4b70276ed
Change-Id: I8a207e30a73d10fe67c0474ff11324ae99e2cec6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41360 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
84 lines
2.5 KiB
Makefile
84 lines
2.5 KiB
Makefile
## SPDX-License-Identifier: GPL-2.0-only
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ifeq ($(CONFIG_SOC_INTEL_DENVERTON_NS),y)
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subdirs-y += ../../../cpu/intel/microcode
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subdirs-y += ../../../cpu/intel/turbo
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subdirs-y += ../../../cpu/x86/lapic
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subdirs-y += ../../../cpu/x86/mtrr
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subdirs-y += ../../../cpu/x86/smm
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subdirs-y += ../../../cpu/x86/tsc
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subdirs-y += ../../../cpu/x86/cache
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bootblock-y += bootblock/bootblock.c
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bootblock-y += spi.c
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bootblock-y += tsc_freq.c
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bootblock-$(CONFIG_CONSOLE_SERIAL) += bootblock/uart.c
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bootblock-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c
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postcar-y += memmap.c
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postcar-y += spi.c
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postcar-y += tsc_freq.c
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postcar-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c
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romstage-y += memmap.c
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romstage-y += reset.c
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romstage-y += ../../../cpu/intel/car/romstage.c
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romstage-y += romstage.c
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romstage-y += tsc_freq.c
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romstage-y += gpio_dnv.c
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romstage-y += gpio.c
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romstage-y += soc_util.c
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romstage-y += spi.c
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romstage-y += fiamux.c
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romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c
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romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
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romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
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ramstage-y += memmap.c
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ramstage-y += systemagent.c
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ramstage-y += reset.c
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ramstage-y += chip.c
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ramstage-y += soc_util.c
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ramstage-y += uart.c
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ramstage-y += xhci.c
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ramstage-y += csme_ie_kt.c
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ramstage-y += lpc.c
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ramstage-y += pmc.c
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ramstage-y += npk.c
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ramstage-y += sata.c
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ramstage-y += cpu.c
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ramstage-y += tsc_freq.c
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ramstage-y += spi.c
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ramstage-y += fiamux.c
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ramstage-y += hob_mem.c
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ramstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c
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ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c
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ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
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ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
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smm-y += pmutil.c
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smm-y += soc_util.c
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smm-y += smihandler.c
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smm-y += tsc_freq.c
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smm-$(CONFIG_SPI_FLASH_SMM) += spi.c
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smm-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c
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verstage-y += memmap.c
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verstage-y += reset.c
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verstage-y += spi.c
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verstage-y += tsc_freq.c
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verstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c
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CPPFLAGS_common += -I$(src)/soc/intel/denverton_ns/include
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##Set FSP binary blobs memory location
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$(call strip_quotes,$(CONFIG_FSP_T_CBFS))-options := -b $(CONFIG_FSP_T_ADDR) --xip
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$(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR) --xip
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$(call strip_quotes,$(CONFIG_FSP_S_CBFS))-options := -b $(CONFIG_FSP_S_ADDR) --xip
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cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-5f-01
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endif ## CONFIG_SOC_INTEL_DENVERTON_NS
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