coreboot-kgpe-d16/spd/lp5
Karthikeyan Ramasubramanian 0b4f49c792 util/spd_tools/spd_gen/lp5: Remove maxSpeed for Sabrina
Firmware component that does memory training already limits the memory
controller to train at 5500 Mbps for all memory parts in Sabrina. Hence
removing this interim SPD change to limit the speed.

BUG=b:238074863
TEST=Build and boot to OS in Skyrim.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I2bc82c7407a97aac282708c3e0bd56ae99a8fc31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66290
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-01 20:30:39 +00:00
..
set-0 spd/lp5: Add SPD for Micron MT62F2G32D4DS-026 2022-07-29 15:00:33 +00:00
set-1 util/spd_tools/spd_gen/lp5: Remove maxSpeed for Sabrina 2022-08-01 20:30:39 +00:00
memory_parts.json spd/lp5: Add SPD for Micron MT62F2G32D4DS-026 2022-07-29 15:00:33 +00:00
platforms_manifest.generated.txt util/spd_tools: Limit memory speed to 5500 Mbps for Sabrina 2022-07-19 15:11:53 +00:00