1aff2e97ea
Change-Id: I29c7d367df7d1ce911f6cd7ed5e5c56865b41dcc Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7063 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
54 lines
1.5 KiB
Text
54 lines
1.5 KiB
Text
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#define BRIGHTNESS_UP \DSPC.BRTU
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#define BRIGHTNESS_DOWN \DSPC.BRTD
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#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x03, // DSDT revision: ACPI v3.0
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"COREv4", // OEM id
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"COREBOOT", // OEM table id
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0x20090419 // OEM revision
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)
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{
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// Some generic macros
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#include "acpi/platform.asl"
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// global NVS and variables
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#include <southbridge/intel/i82801gx/acpi/globalnvs.asl>
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// General Purpose Events
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#include "acpi/gpe.asl"
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <northbridge/intel/i945/acpi/i945.asl>
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#include <southbridge/intel/i82801gx/acpi/ich7.asl>
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}
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}
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/* Chipset specific sleep states */
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#include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
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}
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