d4955f0ade
New AGESA support files will be used for binaryPI platforms as well. Furthermore, some of those should move from split nb/ sb/ directories to soc/, so move support files for the API under drivers/. Change-Id: I549788091de91f61de8b9adc223d52ffb5732235 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
100 lines
2.6 KiB
C
100 lines
2.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/cpu.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <cpu/amd/mtrr.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/mtrr.h>
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#include <northbridge/amd/agesa/agesa_helper.h>
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static void set_range_uc(u32 base, u32 size)
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{
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int i, max_var_mtrrs;
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msr_t msr;
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msr = rdmsr(MTRR_CAP_MSR);
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max_var_mtrrs = msr.lo & MTRR_CAP_VCNT;
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for (i = 0; i < max_var_mtrrs; i++) {
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msr = rdmsr(MTRR_PHYS_MASK(i));
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if (!(msr.lo & MTRR_PHYS_MASK_VALID))
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break;
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}
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if (i == max_var_mtrrs)
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die("Run out of unused MTRRs\n");
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msr.hi = 0;
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msr.lo = base | MTRR_TYPE_UNCACHEABLE;
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wrmsr(MTRR_PHYS_BASE(i), msr);
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msr.hi = (1 << (cpu_phys_address_size() - 32)) - 1;
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msr.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
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wrmsr(MTRR_PHYS_MASK(i), msr);
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}
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void fixup_cbmem_to_UC(int s3resume)
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{
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if (s3resume)
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return;
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/* For normal path, INIT_POST has returned with all
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* memory set WB cacheable. But we need CBMEM as UC
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* to make CAR teardown with invalidation without
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* writeback possible.
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*/
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uintptr_t top_of_ram = (uintptr_t) cbmem_top();
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top_of_ram = ALIGN_UP(top_of_ram, 4 * MiB);
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set_range_uc(top_of_ram - 4 * MiB, 4 * MiB);
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set_range_uc(top_of_ram - 8 * MiB, 4 * MiB);
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}
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void recover_postcar_frame(struct postcar_frame *pcf, int s3resume)
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{
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msr_t base, mask;
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int i;
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/* Replicate non-UC MTRRs as left behind by AGESA.
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*/
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for (i = 0; i < pcf->max_var_mtrrs; i++) {
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mask = rdmsr(MTRR_PHYS_MASK(i));
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base = rdmsr(MTRR_PHYS_BASE(i));
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u32 size = ~(mask.lo & ~0xfff) + 1;
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u8 type = base.lo & 0x7;
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base.lo &= ~0xfff;
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if (!(mask.lo & MTRR_PHYS_MASK_VALID) ||
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(type == MTRR_TYPE_UNCACHEABLE))
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continue;
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postcar_frame_add_mtrr(pcf, base.lo, size, type);
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}
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/* For S3 resume path, INIT_RESUME does not return with
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* memory covering CBMEM set as WB cacheable. For better
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* speed make them WB after CAR teardown.
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*/
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if (s3resume) {
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uintptr_t top_of_ram = (uintptr_t) cbmem_top();
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top_of_ram = ALIGN_DOWN(top_of_ram, 4*MiB);
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postcar_frame_add_mtrr(pcf, top_of_ram - 4*MiB, 4*MiB,
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MTRR_TYPE_WRBACK);
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postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 4*MiB,
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MTRR_TYPE_WRBACK);
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}
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}
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