d4d5e4d3e1
The original comment says it's a Via C3 and not Epia requirement to deliver IOAPIC interrupts on APIC serial bus. Change-Id: I73c55755e0ec1ac5756b4ee7ccdfc8eb93184e4f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/435 Tested-by: build bot (Jenkins) |
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.. | ||
c_start.S | ||
cbfs_and_run.c | ||
cpu.c | ||
exception.c | ||
id.inc | ||
id.lds | ||
ioapic.c | ||
Makefile.inc | ||
pci_ops_auto.c | ||
pci_ops_conf1.c | ||
pci_ops_conf2.c | ||
pci_ops_mmconf.c | ||
romcc_console.c | ||
romstage_console.c | ||
stages.c | ||
walkcbfs.S |