3a0cb458dc
Change-Id: Id404bdab1f2361f1e7d20f7ee72111971863dddf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17736 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
107 lines
3.1 KiB
C
107 lines
3.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <string.h>
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#include <arch/acpi.h>
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#include <arch/ioapic.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <cpu/amd/amdfam10_sysconf.h>
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#include "mb_sysconf.h"
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unsigned long acpi_fill_madt(unsigned long current)
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{
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device_t dev;
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u32 dword;
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u32 gsi_base = 0;
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uint32_t apicid_sp5100;
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uint32_t apicid_sr5650;
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/* create all subtables for processors */
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current = acpi_create_madt_lapics(current);
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if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
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apicid_sp5100 = 0x0;
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else
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apicid_sp5100 = 0x20;
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apicid_sr5650 = apicid_sp5100 + 1;
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/* Write SB700 IOAPIC, only one */
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sp5100,
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IO_APIC_ADDR, gsi_base);
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/* IOAPIC on rs5690 */
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gsi_base += 24; /* SB700 has 24 IOAPIC entries. */
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dev = dev_find_slot(0, PCI_DEVFN(0, 0));
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if (dev) {
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pci_write_config32(dev, 0xF8, 0x1);
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dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sr5650,
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dword, gsi_base);
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}
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/* bus, source, gsirq, flags */
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current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
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current, 0, 0, 2, 0);
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current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
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current, 0, 9, 9, 0xf);
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/* create all subtables for processors */
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current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 0, 1);
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/* 1: LINT1 connect to NMI */
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return current;
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}
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unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current)
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{
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uint8_t *p;
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uint32_t apicid_sp5100;
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uint32_t apicid_sr5650;
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if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
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apicid_sp5100 = 0x0;
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else
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apicid_sp5100 = 0x20;
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apicid_sr5650 = apicid_sp5100 + 1;
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/* Describe NB IOAPIC */
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p = (uint8_t *)current;
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p[0] = 0x48; /* Entry type */
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p[1] = 0; /* Device */
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p[2] = 0; /* Bus */
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p[3] = 0x0; /* Data */
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p[4] = apicid_sr5650; /* IOAPIC ID */
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p[5] = 0x1; /* Device 0 Function 1 */
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p[6] = 0x0; /* Northbridge bus */
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p[7] = 0x1; /* Variety */
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current += 8;
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/* Describe SB IOAPIC */
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p = (uint8_t *)current;
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p[0] = 0x48; /* Entry type */
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p[1] = 0; /* Device */
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p[2] = 0; /* Bus */
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p[3] = 0xd7; /* Data */
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p[4] = apicid_sp5100; /* IOAPIC ID */
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p[5] = 0x14 << 3; /* Device 0x14 Function 0 */
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p[6] = 0x0; /* Southbridge bus */
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p[7] = 0x1; /* Variety */
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current += 8;
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return current;
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}
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