1236b84234
Correct some whitespace inconsistencies introduced in the
following commit.
commit d7bd4eb003
Author: Stefan Reinauer <reinauer@chromium.org>
Date: Mon Feb 11 11:11:36 2013 -0800
Add support for "Butterfly" Chromebook
Reviewed-on: http://review.coreboot.org/2359
Change-Id: Ifeda7eb29ddf855cdfea41ddbd685441ede55756
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2374
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
304 lines
12 KiB
C
304 lines
12 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef BUTTERFLY_GPIO_H
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#define BUTTERFLY_GPIO_H
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#include "southbridge/intel/bd82x6x/gpio.h"
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const struct pch_gpio_set1 pch_gpio_set1_mode = {
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.gpio0 = GPIO_MODE_NONE, /* Unused */
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.gpio1 = GPIO_MODE_NONE, /* Unused */
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.gpio2 = GPIO_MODE_NONE, /* Unused */
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.gpio3 = GPIO_MODE_NONE, /* Unused */
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.gpio4 = GPIO_MODE_NATIVE, /* Native - TPSINT# for TP SMBus IRQ */
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.gpio5 = GPIO_MODE_NONE, /* Unused */
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.gpio6 = GPIO_MODE_GPIO, /* Input - BOARD_ID4 */
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.gpio7 = GPIO_MODE_GPIO, /* Input - BOARD_ID5 */
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.gpio8 = GPIO_MODE_GPIO, /* Output - BT on/off */
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.gpio9 = GPIO_MODE_NONE, /* Unused */
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.gpio10 = GPIO_MODE_NONE, /* Unused */
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.gpio11 = GPIO_MODE_GPIO, /* Input - TP WAKEUP Event */
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.gpio12 = GPIO_MODE_NONE, /* Unused */
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.gpio13 = GPIO_MODE_GPIO, /* Input - SCI from EC */
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.gpio14 = GPIO_MODE_GPIO, /* Output - AOAC WLAN power control */
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.gpio15 = GPIO_MODE_GPIO, /* Unused - Do not control WLAN*/
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.gpio16 = GPIO_MODE_NONE, /* Unused */
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.gpio17 = GPIO_MODE_GPIO, /* Input - DGPU_PWROK */
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.gpio18 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ1# LAN clock pin*/
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.gpio19 = GPIO_MODE_GPIO, /* Input - Boot BIOS Selection 0 */
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.gpio20 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ2# SDCard clock pin */
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.gpio21 = GPIO_MODE_GPIO, /* Input - EC_ENTERING_RW for Google OS */
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.gpio22 = GPIO_MODE_GPIO, /* Input - BIOS RECOVERY */
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.gpio23 = GPIO_MODE_NONE, /* Unused */
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.gpio24 = GPIO_MODE_GPIO, /* Output - DGPU_HOLD_RST# */
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.gpio25 = GPIO_MODE_NONE, /* Unused */
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.gpio26 = GPIO_MODE_NONE, /* Unused */
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.gpio27 = GPIO_MODE_NONE, /* Unused */
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.gpio28 = GPIO_MODE_NONE, /* Unused */
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.gpio29 = GPIO_MODE_NONE, /* Unused */
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.gpio30 = GPIO_MODE_NATIVE, /* Native - SUSWARN_EC# */
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.gpio31 = GPIO_MODE_NONE, /* Unused */
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};
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const struct pch_gpio_set1 pch_gpio_set1_direction = {
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.gpio0 = GPIO_DIR_INPUT, /* Unused */
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.gpio1 = GPIO_DIR_INPUT, /* Unused */
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.gpio2 = GPIO_DIR_INPUT, /* Unused */
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.gpio3 = GPIO_DIR_INPUT, /* Unused */
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.gpio4 = GPIO_DIR_INPUT, /* Native */
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.gpio5 = GPIO_DIR_INPUT, /* Unused */
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.gpio6 = GPIO_DIR_INPUT, /* Input */
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.gpio7 = GPIO_DIR_INPUT, /* Input */
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.gpio8 = GPIO_DIR_INPUT, /* Output HIGH - set in mainboard.c */
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.gpio9 = GPIO_DIR_INPUT, /* Unused */
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.gpio10 = GPIO_DIR_INPUT, /* Unused */
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.gpio11 = GPIO_DIR_INPUT, /* Input */
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.gpio12 = GPIO_DIR_INPUT, /* Unused */
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.gpio13 = GPIO_DIR_INPUT, /* Input */
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.gpio14 = GPIO_DIR_OUTPUT, /* Output HIGH */
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.gpio15 = GPIO_DIR_INPUT, /* Unused */
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.gpio16 = GPIO_DIR_INPUT, /* Unused */
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.gpio17 = GPIO_DIR_INPUT, /* Input */
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.gpio18 = GPIO_DIR_INPUT, /* Native */
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.gpio19 = GPIO_DIR_INPUT, /* Input */
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.gpio20 = GPIO_DIR_INPUT, /* Native */
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.gpio21 = GPIO_DIR_INPUT, /* Input */
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.gpio22 = GPIO_DIR_INPUT, /* Input */
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.gpio23 = GPIO_DIR_INPUT, /* Unused */
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.gpio24 = GPIO_DIR_OUTPUT, /* Output HIGH */
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.gpio25 = GPIO_DIR_INPUT, /* Unused */
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.gpio26 = GPIO_DIR_INPUT, /* Unused */
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.gpio27 = GPIO_DIR_INPUT, /* Unused */
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.gpio28 = GPIO_DIR_INPUT, /* Unused */
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.gpio29 = GPIO_DIR_INPUT, /* Unused */
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.gpio30 = GPIO_DIR_INPUT, /* Native */
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.gpio31 = GPIO_DIR_INPUT, /* Unused */
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};
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const struct pch_gpio_set1 pch_gpio_set1_level = {
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.gpio0 = GPIO_LEVEL_LOW, /* Unused */
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.gpio1 = GPIO_LEVEL_LOW, /* Unused */
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.gpio2 = GPIO_LEVEL_LOW, /* Unused */
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.gpio3 = GPIO_LEVEL_LOW, /* Unused */
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.gpio4 = GPIO_LEVEL_LOW, /* Native */
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.gpio5 = GPIO_LEVEL_LOW, /* Unused */
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.gpio6 = GPIO_LEVEL_LOW, /* Input */
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.gpio7 = GPIO_LEVEL_LOW, /* Input */
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.gpio8 = GPIO_LEVEL_HIGH, /* Output HIGH - set in mainboard.c */
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.gpio9 = GPIO_LEVEL_LOW, /* Unused */
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.gpio10 = GPIO_LEVEL_LOW, /* Unused */
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.gpio11 = GPIO_LEVEL_LOW, /* Input */
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.gpio12 = GPIO_LEVEL_LOW, /* Unused */
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.gpio13 = GPIO_LEVEL_LOW, /* Input */
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.gpio14 = GPIO_LEVEL_HIGH, /* Output HIGH */
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.gpio15 = GPIO_LEVEL_HIGH, /* Unused */
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.gpio16 = GPIO_LEVEL_LOW, /* Unused */
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.gpio17 = GPIO_LEVEL_LOW, /* Input */
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.gpio18 = GPIO_LEVEL_LOW, /* Native */
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.gpio19 = GPIO_LEVEL_LOW, /* Input */
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.gpio20 = GPIO_LEVEL_LOW, /* Native */
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.gpio21 = GPIO_LEVEL_LOW, /* Input */
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.gpio22 = GPIO_LEVEL_LOW, /* Input */
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.gpio23 = GPIO_LEVEL_LOW, /* Unused */
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.gpio24 = GPIO_LEVEL_HIGH, /* Output HIGH */
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.gpio25 = GPIO_LEVEL_LOW, /* Unused */
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.gpio26 = GPIO_LEVEL_LOW, /* Unused */
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.gpio27 = GPIO_LEVEL_LOW, /* Unused */
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.gpio28 = GPIO_LEVEL_LOW, /* Unused */
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.gpio29 = GPIO_LEVEL_LOW, /* Unused */
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.gpio30 = GPIO_LEVEL_LOW, /* Native */
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.gpio31 = GPIO_LEVEL_LOW, /* Unused */
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};
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const struct pch_gpio_set1 pch_gpio_set1_invert = {
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.gpio11 = GPIO_INVERT, /* invert touchpad wakeup pin */
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.gpio13 = GPIO_INVERT, /* invert EC SCI pin */
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};
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const struct pch_gpio_set2 pch_gpio_set2_mode = {
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.gpio32 = GPIO_MODE_NATIVE, /* Native - Connect to EC Clock Run */
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.gpio33 = GPIO_MODE_GPIO, /* Input - (Google protect BIOS ROM) */
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.gpio34 = GPIO_MODE_NONE, /* Unused */
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.gpio35 = GPIO_MODE_NONE, /* Unused */
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.gpio36 = GPIO_MODE_GPIO, /* Output - DGPU_PWR_EN */
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.gpio37 = GPIO_MODE_GPIO, /* Input - FDI TERM / VOLTAGE OVERRIDE */
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.gpio38 = GPIO_MODE_GPIO, /* Input - MFG_MODE test */
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.gpio39 = GPIO_MODE_GPIO, /* Input - DGPU_PRSNT */
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.gpio40 = GPIO_MODE_NONE, /* Unused */
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.gpio41 = GPIO_MODE_NONE, /* Unused */
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.gpio42 = GPIO_MODE_NONE, /* Unused */
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.gpio43 = GPIO_MODE_NONE, /* Unused */
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.gpio44 = GPIO_MODE_GPIO, /* Input - BOARD_ID0 */
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.gpio45 = GPIO_MODE_GPIO, /* Input - BOARD_ID1 */
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.gpio46 = GPIO_MODE_GPIO, /* Input - BOARD_ID2 */
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.gpio47 = GPIO_MODE_NATIVE, /* Native - PEGA_GPU clock request */
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.gpio48 = GPIO_MODE_NONE, /* Unused */
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.gpio49 = GPIO_MODE_NONE, /* Unused */
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.gpio50 = GPIO_MODE_NONE, /* Unused */
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.gpio51 = GPIO_MODE_GPIO, /* Input - Boot BIOS Selection 1 */
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.gpio52 = GPIO_MODE_GPIO, /* Input - Google recovery, Pull up +3V */
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.gpio53 = GPIO_MODE_GPIO, /* Output - G Sensor LED */
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.gpio54 = GPIO_MODE_GPIO, /* Input - Google Development */
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.gpio55 = GPIO_MODE_GPIO, /* Input - Top-Block Swap Override */
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.gpio56 = GPIO_MODE_NONE, /* Unused */
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.gpio57 = GPIO_MODE_GPIO, /* Input - SV_DET */
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.gpio58 = GPIO_MODE_NONE, /* Unused */
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.gpio59 = GPIO_MODE_NONE, /* Unused */
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.gpio60 = GPIO_MODE_NONE, /* GPO - DRAMRST_CNTRL_PCH */
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.gpio61 = GPIO_MODE_NONE, /* Unused */
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.gpio62 = GPIO_MODE_NATIVE, /* Native - Connect to EC 32.768KHz */
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.gpio63 = GPIO_MODE_NATIVE, /* Native - SLP_S5 */
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};
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const struct pch_gpio_set2 pch_gpio_set2_direction = {
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.gpio32 = GPIO_DIR_INPUT, /* Native */
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.gpio33 = GPIO_DIR_INPUT, /* Input */
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.gpio34 = GPIO_DIR_INPUT, /* Unused */
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.gpio35 = GPIO_DIR_INPUT, /* Unused */
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.gpio36 = GPIO_DIR_OUTPUT, /* Output HIGH */
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.gpio37 = GPIO_DIR_INPUT, /* Input */
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.gpio38 = GPIO_DIR_INPUT, /* Input */
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.gpio39 = GPIO_DIR_INPUT, /* Input */
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.gpio40 = GPIO_DIR_INPUT, /* Unused */
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.gpio41 = GPIO_DIR_INPUT, /* Unused */
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.gpio42 = GPIO_DIR_INPUT, /* Unused */
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.gpio43 = GPIO_DIR_INPUT, /* Unused */
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.gpio44 = GPIO_DIR_INPUT, /* Input */
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.gpio45 = GPIO_DIR_INPUT, /* Input */
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.gpio46 = GPIO_DIR_INPUT, /* Input */
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.gpio47 = GPIO_DIR_INPUT, /* Native */
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.gpio48 = GPIO_DIR_INPUT, /* Unused */
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.gpio49 = GPIO_DIR_INPUT, /* Unused */
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.gpio50 = GPIO_DIR_INPUT, /* Unused */
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.gpio51 = GPIO_DIR_INPUT, /* Input */
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.gpio52 = GPIO_DIR_INPUT, /* Input */
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.gpio53 = GPIO_DIR_OUTPUT, /* Input */
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.gpio54 = GPIO_DIR_INPUT, /* Input */
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.gpio55 = GPIO_DIR_INPUT, /* Input */
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.gpio56 = GPIO_DIR_INPUT, /* Unused */
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.gpio57 = GPIO_DIR_INPUT, /* Input */
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.gpio58 = GPIO_DIR_INPUT, /* Unused */
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.gpio59 = GPIO_DIR_INPUT, /* Unused */
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.gpio60 = GPIO_DIR_OUTPUT, /* Output HIGH */
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.gpio61 = GPIO_DIR_INPUT, /* Unused */
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.gpio62 = GPIO_DIR_INPUT, /* Native */
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.gpio63 = GPIO_DIR_INPUT, /* Native */
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};
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const struct pch_gpio_set2 pch_gpio_set2_level = {
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.gpio32 = GPIO_LEVEL_LOW, /* Native */
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.gpio33 = GPIO_LEVEL_LOW, /* Input */
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.gpio34 = GPIO_LEVEL_LOW, /* Unused */
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.gpio35 = GPIO_LEVEL_LOW, /* Unused */
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.gpio36 = GPIO_LEVEL_HIGH, /* Output HIGH */
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.gpio37 = GPIO_LEVEL_LOW, /* Input */
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.gpio38 = GPIO_LEVEL_LOW, /* Input */
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.gpio39 = GPIO_LEVEL_LOW, /* Input */
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.gpio40 = GPIO_LEVEL_LOW, /* Unused */
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.gpio41 = GPIO_LEVEL_LOW, /* Unused */
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.gpio42 = GPIO_LEVEL_LOW, /* Unused */
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.gpio43 = GPIO_LEVEL_LOW, /* Unused */
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.gpio44 = GPIO_LEVEL_LOW, /* Input */
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.gpio45 = GPIO_LEVEL_LOW, /* Input */
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.gpio46 = GPIO_LEVEL_LOW, /* Input */
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.gpio47 = GPIO_LEVEL_LOW, /* Native */
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.gpio48 = GPIO_LEVEL_LOW, /* Unused */
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.gpio49 = GPIO_LEVEL_LOW, /* Unused */
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.gpio50 = GPIO_LEVEL_LOW, /* Unused */
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.gpio51 = GPIO_LEVEL_LOW, /* Input */
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.gpio52 = GPIO_LEVEL_LOW, /* Input */
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.gpio53 = GPIO_LEVEL_HIGH, /* Input */
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.gpio54 = GPIO_LEVEL_LOW, /* Input */
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.gpio55 = GPIO_LEVEL_LOW, /* Input */
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.gpio56 = GPIO_LEVEL_LOW, /* Unused */
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.gpio57 = GPIO_LEVEL_LOW, /* Input */
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.gpio58 = GPIO_LEVEL_LOW, /* Unused */
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.gpio59 = GPIO_LEVEL_LOW, /* Unused */
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.gpio60 = GPIO_LEVEL_HIGH, /* Output HIGH */
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.gpio61 = GPIO_LEVEL_LOW, /* Unused */
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.gpio62 = GPIO_LEVEL_LOW, /* Native */
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.gpio63 = GPIO_LEVEL_LOW, /* Native */
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};
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const struct pch_gpio_set3 pch_gpio_set3_mode = {
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.gpio64 = GPIO_MODE_NONE, /* Unused */
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.gpio65 = GPIO_MODE_NONE, /* Unused */
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.gpio66 = GPIO_MODE_NONE, /* Unused */
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.gpio67 = GPIO_MODE_NONE, /* Unused */
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.gpio68 = GPIO_MODE_GPIO, /* Input - DGPU_PWR_EN */
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.gpio69 = GPIO_MODE_NONE, /* Unused */
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.gpio70 = GPIO_MODE_NONE, /* Unused */
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.gpio71 = GPIO_MODE_NONE, /* Unused */
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.gpio72 = GPIO_MODE_NONE, /* Unused */
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.gpio73 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ0# WLAN clock request */
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.gpio74 = GPIO_MODE_NONE, /* Unused */
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.gpio75 = GPIO_MODE_GPIO, /* Input - SMB_ME1_DAT */
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};
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const struct pch_gpio_set3 pch_gpio_set3_direction = {
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.gpio64 = GPIO_DIR_INPUT, /* Unused */
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.gpio65 = GPIO_DIR_INPUT, /* Unused */
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.gpio66 = GPIO_DIR_INPUT, /* Unused */
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.gpio67 = GPIO_DIR_INPUT, /* Unused */
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.gpio68 = GPIO_DIR_INPUT, /* Input */
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.gpio69 = GPIO_DIR_INPUT, /* Unused */
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.gpio70 = GPIO_DIR_INPUT, /* Unused */
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.gpio71 = GPIO_DIR_INPUT, /* Unused */
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.gpio72 = GPIO_DIR_INPUT, /* Unused */
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.gpio73 = GPIO_DIR_INPUT, /* Native */
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.gpio74 = GPIO_DIR_INPUT, /* Unused */
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.gpio75 = GPIO_DIR_INPUT, /* Input */
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};
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const struct pch_gpio_set3 pch_gpio_set3_level = {
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.gpio64 = GPIO_LEVEL_LOW, /* Unused */
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.gpio65 = GPIO_LEVEL_LOW, /* Unused */
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.gpio66 = GPIO_LEVEL_LOW, /* Unused */
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.gpio67 = GPIO_LEVEL_LOW, /* Unused */
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.gpio68 = GPIO_LEVEL_LOW, /* Input */
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.gpio69 = GPIO_LEVEL_LOW, /* Unused */
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.gpio70 = GPIO_LEVEL_LOW, /* Unused */
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.gpio71 = GPIO_LEVEL_LOW, /* Unused */
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.gpio72 = GPIO_LEVEL_LOW, /* Unused */
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.gpio73 = GPIO_LEVEL_LOW, /* Native */
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.gpio74 = GPIO_LEVEL_LOW, /* Unused */
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.gpio75 = GPIO_LEVEL_LOW, /* Input */
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};
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const struct pch_gpio_map butterfly_gpio_map = {
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.set1 = {
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.mode = &pch_gpio_set1_mode,
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.direction = &pch_gpio_set1_direction,
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.level = &pch_gpio_set1_level,
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.invert = &pch_gpio_set1_invert,
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},
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.set2 = {
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.mode = &pch_gpio_set2_mode,
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.direction = &pch_gpio_set2_direction,
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.level = &pch_gpio_set2_level,
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},
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.set3 = {
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.mode = &pch_gpio_set3_mode,
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.direction = &pch_gpio_set3_direction,
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.level = &pch_gpio_set3_level,
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},
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};
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#endif
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