40acfe7f77
The CBFS mcache size default was eyeballed to what should be "hopefully enough" for most users, but some recent Chrome OS devices have already hit the limit. Since most current (and probably all future) x86 chipsets likely have the CAR space to spare, let's just double the size default for all supporting chipsets right now so that we hopefully won't run into these issues again any time soon. The CBFS_MCACHE_RW_PERCENTAGE default for CHROMEOS was set to 25 under the assumption that Chrome OS images have historically always had a lot more files in their RO CBFS than the RW (because l10n assets were only in RO). Unfortunately, this has recently changed with the introduction of updateable assets. While hopefully not that many boards will need these, the whole idea is that you won't know whether you need them yet at the time the RO image is frozen, and mcache layout parameters cannot be changed in an RW update. So better to use the normal 50/50 split on Chrome OS devices going forward so we are prepared for the eventuality of needing RW assets again. The RW percentage should really also be menuconfig-controllable, because this is something the user may want to change on the fly depending on their payload requirements. Move the option to the vboot Kconfigs because it also kinda belongs there anyway and this makes it fit in better in menuconfig. (I haven't made the mcache size menuconfig-controllable because if anyone needs to increase this, they can just override the default in the chipset Kconfig for everyone using that chipset, under the assumption that all boards of that chipset have the same amount of available CAR space and there's no reason not to use up the available space. This seems more in line with how this would work on non-x86 platforms that define this directly in their memlayout.ld.) Also add explicit warnings to both options that they mustn't be changed in an RW update to an older RO image. BUG=b:187561710 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I046ae18c9db9a5d682384edde303c07e0be9d790 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
100 lines
2.3 KiB
Text
100 lines
2.3 KiB
Text
config MISSING_BOARD_RESET
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bool
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help
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Selected by boards that don't provide a do_board_reset()
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implementation. This activates a stub that logs the missing
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board reset and halts execution.
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config RAMSTAGE_ADA
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bool
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help
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Selected by features that use Ada code in ramstage.
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config RAMSTAGE_LIBHWBASE
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bool
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select RAMSTAGE_ADA
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help
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Selected by features that require `libhwbase` in ramstage.
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config FLATTENED_DEVICE_TREE
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bool
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help
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Selected by features that require to parse and manipulate a flattened
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devicetree in ramstage.
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config HAVE_SPD_IN_CBFS
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bool
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help
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If enabled, add support for adding spd.hex files in cbfs as spd.bin
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and locating it runtime to load SPD.
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config DIMM_MAX
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int
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default 4
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help
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Total number of memory DIMM slots available on motherboard.
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It is multiplication of number of channel to number of DIMMs per
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channel
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config DIMM_SPD_SIZE
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int
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default 256
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help
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Total SPD size that will be used for DIMM.
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Ex: DDR3 256, DDR4 512.
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config SPD_READ_BY_WORD
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bool
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config SPD_CACHE_IN_FMAP
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bool
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default n
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help
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Enables capability to cache DIMM SPDs in a dedicated FMAP region
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to speed loading of SPD data. Currently requires board-level
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romstage implementation to read/write/utilize cached SPD data.
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When the default FMAP is used, will create a region named RW_SPD_CACHE
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to store the cached SPD data.
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config SPD_CACHE_FMAP_NAME
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string
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depends on SPD_CACHE_IN_FMAP
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default "RW_SPD_CACHE"
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help
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Name of the FMAP region created in the default FMAP to cache SPD data.
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if RAMSTAGE_LIBHWBASE
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config HWBASE_DYNAMIC_MMIO
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def_bool y
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config HWBASE_DEFAULT_MMCONF
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hex
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default MMCONF_BASE_ADDRESS
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config HWBASE_DIRECT_PCIDEV
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def_bool y
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endif
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config NO_FMAP_CACHE
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bool
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help
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If your platform really doesn't want to use an FMAP cache (e.g. due to
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space constraints), you can select this to disable warnings and save
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a bit more code.
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config ESPI_DEBUG
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bool
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help
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This option enables eSPI library helper functions for displaying debug
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information.
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config NO_CBFS_MCACHE
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bool
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help
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Disables the CBFS metadata cache. This means that your platform does
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not need to provide a CBFS_MCACHE section in memlayout and can save
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the associated CAR/SRAM size. In that case every single CBFS file
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lookup must re-read the same CBFS directory entries from flash to find
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the respective file.
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