436f99b72a
which is normally set to 0x10 (the current default) and set to 0x80 (the current alternative) where necessary (if romstraps get in the way). For Kconfig, the special case is set per southbridge (as these define the necessity for this workaround), for newconfig it's added to each single board. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4962 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
241 lines
7.8 KiB
Text
241 lines
7.8 KiB
Text
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007 AMD
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## (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
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## Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
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## (Thanks to LSRA University of Mannheim for their support)
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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## CONFIG_XIP_ROM_SIZE must be a power of 2.
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default CONFIG_XIP_ROM_SIZE = 64 * 1024
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include /config/failovercalculation.lb
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arch i386 end
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driver mainboard.o
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# Needed by irq_tables and mptable and acpi_tables.
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object get_bus_conf.o
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if CONFIG_GENERATE_MP_TABLE object mptable.o end
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if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
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if CONFIG_USE_INIT
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makerule ./auto.o
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depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
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end
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else
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makerule ./auto.inc
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depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
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action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
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action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
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end
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end
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if CONFIG_HAVE_FAILOVER_BOOT
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if CONFIG_USE_FAILOVER_IMAGE
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mainboardinit cpu/x86/16bit/entry16.inc
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ldscript /cpu/x86/16bit/entry16.lds
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end
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else
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if CONFIG_USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/entry16.inc
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ldscript /cpu/x86/16bit/entry16.lds
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end
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end
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mainboardinit cpu/x86/32bit/entry32.inc
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if CONFIG_USE_INIT
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ldscript /cpu/x86/32bit/entry32.lds
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ldscript /cpu/amd/car/cache_as_ram.lds
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end
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if CONFIG_HAVE_FAILOVER_BOOT
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if CONFIG_USE_FAILOVER_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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else
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if CONFIG_USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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end
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# Include an ID string (for safe flashing).
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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# ROMSTRAP table for CK804.
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if CONFIG_HAVE_FAILOVER_BOOT
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if CONFIG_USE_FAILOVER_IMAGE
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mainboardinit southbridge/nvidia/ck804/romstrap.inc
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ldscript /southbridge/nvidia/ck804/romstrap.lds
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end
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else
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if CONFIG_USE_FALLBACK_IMAGE
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mainboardinit southbridge/nvidia/ck804/romstrap.inc
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ldscript /southbridge/nvidia/ck804/romstrap.lds
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end
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end
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mainboardinit cpu/amd/car/cache_as_ram.inc
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if CONFIG_HAVE_FAILOVER_BOOT
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if CONFIG_USE_FAILOVER_IMAGE
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ldscript /arch/i386/lib/failover_failover.lds
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end
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else
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if CONFIG_USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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end
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end
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if CONFIG_USE_INIT
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initobject auto.o
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else
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mainboardinit ./auto.inc
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end
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config chip.h
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chip northbridge/amd/amdk8/root_complex # Root complex
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device apic_cluster 0 on # APIC cluster
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chip cpu/amd/socket_939 # Socket 939 CPU
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device apic 0 on end # APIC
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end
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end
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device pci_domain 0 on # PCI domain
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chip northbridge/amd/amdk8 # mc0
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device pci 18.0 on # Northbridge
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# Devices on link 0, link 0 == LDT 0
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chip southbridge/nvidia/ck804 # Southbridge
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device pci 0.0 on end # HT
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device pci 1.0 on # LPC
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chip superio/ite/it8712f # Super I/O
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device pnp 2e.0 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.2 off # Com2 (N/A on this board)
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.3 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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drq 0x74 = 3
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end
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device pnp 2e.4 on # Environment controller
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io 0x60 = 0x290
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io 0x62 = 0x0000
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irq 0x70 = 0x00
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end
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device pnp 2e.5 on # PS/2 keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x71 = 2
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end
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device pnp 2e.6 on # PS/2 mouse
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irq 0x70 = 12
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irq 0x71 = 2
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end
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device pnp 2e.7 on # GPIO config
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io 0x60 = 0x0800
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# Set GPIO 1 & 2
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io 0x25 = 0x0000
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# Set GPIO 3 & 4
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io 0x27 = 0x2540
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# GPIO Polarity for Set 3
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io 0xb2 = 0x2100
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# GPIO Pin Internal Pull up for Set 3
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io 0xba = 0x0100
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# Simple I/O register config
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io 0xc0 = 0x0000
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io 0xc2 = 0x2540
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io 0xc8 = 0x0000
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io 0xca = 0x0500
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end
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device pnp 2e.8 on # Midi port
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io 0x60 = 0x300
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irq 0x70 = 10
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end
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device pnp 2e.9 on # Game port
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io 0x60 = 0x201
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end
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device pnp 2e.a off # IR (N/A on this board)
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io 0x60 = 0x310
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irq 0x70 = 11
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end
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end
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end
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device pci 1.1 on # SM 0
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# chip drivers/generic/generic #dimm 0-0-0
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# device i2c 50 on end
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# end
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# chip drivers/generic/generic #dimm 0-0-1
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# device i2c 51 on end
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# end
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# chip drivers/generic/generic #dimm 0-1-0
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# device i2c 52 on end
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# end
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# chip drivers/generic/generic #dimm 0-1-1
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# device i2c 53 on end
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# end
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# chip drivers/generic/generic #dimm 1-0-0
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# device i2c 54 on end
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# end
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# chip drivers/generic/generic #dimm 1-0-1
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# device i2c 55 on end
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# end
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# chip drivers/generic/generic #dimm 1-1-0
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# device i2c 56 on end
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# end
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# chip drivers/generic/generic #dimm 1-1-1
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# device i2c 57 on end
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# end
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end
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device pci 2.0 on end # USB 1.1
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device pci 2.1 on end # USB 2
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device pci 4.0 on end # Onboard audio (ACI)
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device pci 4.1 off end # Onboard modem (MCI), N/A
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device pci 6.0 on end # IDE
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device pci 7.0 on end # SATA 1
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device pci 8.0 on end # SATA 0
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device pci 9.0 on end # PCI
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device pci a.0 on end # NIC
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device pci b.0 on end # PCI E 3
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device pci c.0 on end # PCI E 2
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device pci d.0 on end # PCI E 1
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device pci e.0 on end # PCI E 0
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register "ide0_enable" = "1"
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register "ide1_enable" = "1"
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register "sata0_enable" = "1"
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register "sata1_enable" = "1"
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# register "mac_eeprom_smbus" = "3"
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# register "mac_eeprom_addr" = "0x51"
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end
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end
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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end
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end
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end
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