13c8d024c2
There are clock settings for usb in mt8195 and mt8188, so we add a new function which is implemented in pll.c to do this. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I40b358b197541bc5281645879553340059829db3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65750 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
39 lines
911 B
C
39 lines
911 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/mmio.h>
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#include <soc/infracfg.h>
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#include <soc/pll.h>
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#include <soc/usb.h>
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void mtk_usb_prepare(void)
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{
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mt_pll_set_usb_clock();
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}
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void mtk_usb_adjust_phy_shift(void)
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{
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u32 phy_set_val, write_val;
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struct ssusb_sif_port *phy = (void *)(SSUSB_SIF_BASE);
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SET32_BITFIELDS(&phy->u3phyd.phyd_reserved,
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AUTO_LOAD_DIS, 1);
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phy_set_val = read32((void *)USB_PHY_SETTING_REG);
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/* TX imp */
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write_val = (phy_set_val & TX_IMP_MASK) >> TX_IMP_SHIFT;
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SET32_BITFIELDS(&phy->u3phyd.phyd_cal0,
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TX_IMP_CAL, write_val,
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TX_IMP_CAL_EN, 1);
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/* RX imp */
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write_val = (phy_set_val & RX_IMP_MASK) >> RX_IMP_SHIFT;
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SET32_BITFIELDS(&phy->u3phyd.phyd_cal1,
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RX_IMP_CAL, write_val,
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RX_IMP_CAL_EN, 1);
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/* Intr_cal */
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write_val = (phy_set_val & INTR_CAL_MASK) >> INTR_CAL_SHIFT;
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SET32_BITFIELDS(&phy->u3phya.phya_reg0,
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INTR_CAL, write_val);
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}
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