a46a712610
In the file `COPYING` in the coreboot repository and upstream [1]
just one space is used.
The following command was used to convert all files.
$ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/'
[1] http://www.gnu.org/licenses/gpl-2.0.txt
Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2490
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
82 lines
2.5 KiB
C
82 lines
2.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2004 Ronald G. Minnich
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include "i82801dx.h"
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typedef struct southbridge_intel_i82801dx_config config_t;
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static void ide_init(struct device *dev)
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{
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/* Get the chip configuration */
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config_t *config = dev->chip_info;
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/* Enable IDE devices so the Linux IDE driver will work. */
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uint16_t ideTimingConfig;
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ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI);
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ideTimingConfig &= ~IDE_DECODE_ENABLE;
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if (!config || config->ide0_enable) {
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/* Enable primary IDE interface. */
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ideTimingConfig |= IDE_DECODE_ENABLE;
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printk(BIOS_DEBUG, "IDE0: Primary IDE interface is enabled\n");
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} else {
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printk(BIOS_INFO, "IDE0: Primary IDE interface is disabled\n");
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}
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pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig);
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ideTimingConfig = pci_read_config16(dev, IDE_TIM_SEC);
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ideTimingConfig &= ~IDE_DECODE_ENABLE;
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if (!config || config->ide1_enable) {
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/* Enable secondary IDE interface. */
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ideTimingConfig |= IDE_DECODE_ENABLE;
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printk(BIOS_DEBUG, "IDE1: Secondary IDE interface is enabled\n");
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} else {
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printk(BIOS_INFO, "IDE1: Secondary IDE interface is disabled\n");
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}
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pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig);
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}
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static struct device_operations ide_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = ide_init,
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.scan_bus = 0,
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.enable = i82801dx_enable,
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};
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/* 82801DB */
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static const struct pci_driver i82801db_ide __pci_driver = {
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.ops = &ide_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = 0x24cb,
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};
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/* 82801DBM */
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static const struct pci_driver i82801dbm_ide __pci_driver = {
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.ops = &ide_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = 0x24ca,
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};
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