Werner Zeh d6798e96fc mb/siemens/mc_ehl1: Clean up PCIe root port settings in devicetree ... PCIe root ports #5 (00:1c.4) and #6 (00:1c.5) are not used on this mainboard and are not routed either, so remove them from the devicetree completely. PCIe root port #7 (00:1c.6) is connected and used. Add the missing settings for L1 substates and latency reporting to disable these features for this port as well. Change-Id: I06f59f0369ffcd958b5fe12bb3c646d37103811f Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58568 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-11-02 08:14:05 +00:00
..
chili	mb/siemens/chili: Drop redundant Kconfig select	2021-10-27 15:04:26 +00:00
mc_apl1	mb/*: Specify type of VARIANT_DIR once	2021-07-26 14:07:38 +00:00
mc_ehl	mb/siemens/mc_ehl1: Clean up PCIe root port settings in devicetree	2021-11-02 08:14:05 +00:00
Kconfig	mb/*/Kconfig: Factor out MAINBOARD_VENDOR	2020-03-03 10:15:22 +00:00
Kconfig.name