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Duncan Laurie d67c5dbf06 slippy: Add on-board devices and configure GPIO irq/wake
Add the onboard I2C devices for Slippy trackpad/lightsensor
and generate SMBIOS Type41 tables for them.

Add ACPI device for the trackpad to expose the interrupt map
to the OS so it can be used.

Configure interrupt GPIOs as PIRQ type and wake GPIOs as
just standard input type.  The wake GPIO is reconfigured as
ACPI SCI in the specific device _DSW method.  This prevents
the wake GPIO from generating a flood of SCI at runtime.

LTE_WAKE_L_Q and WLAN_WAKE_L_Q are left as ACPI SCI as these
are not repurposed interrupt pins so they are not generated
at runtime.

SIM_DET and ALS_INT_L are set as input since we don't have an
interrupt handler for them.

tested on slippy with trackpad with additional
kernel changes to chromeos_laptop.c to initialize devices.

1) Ensure trackpad interrupt is functional and that there
is not a flood of ACPI SCI when trackpad does interrupt:
  9:          1          0          0          0   IO-APIC-fasteoi   acpi
 37:        421          0          0          0   IO-APIC-fasteoi   cyapa

2) Ensure that devices are exposed as wake capable:
Device  S-state   Status   Sysfs node
TPAD      S3    *enabled   pnp:00:00
TSCR      S3    *disabled  pnp:00:01

3) Ensure that trackpad can wake from S3 by default, but
that it does not cause an immediate wake when entering suspend.

4) Ensure that trackpad can be disabled as a wake source with
echo TPAD > /proc/acpi/wakeup

Change-Id: Id562d20b54eeefec56040b8f70ef238911312628
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56622
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4190
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-11-25 23:45:44 +01:00
3rdparty@aebd21811d AMD Yangtze: Update 3rdparty hash for new blobs 2013-07-18 20:06:55 +02:00
documentation Remove NRV2B compression support 2013-08-31 08:58:37 +02:00
payloads libpayload: Fix xcompile 2013-11-25 23:36:27 +01:00
src slippy: Add on-board devices and configure GPIO irq/wake 2013-11-25 23:45:44 +01:00
util cbfstool: check potential microcode update earlier 2013-11-25 23:24:57 +01:00
.gitignore .gitignore: Properly ignore KDevelop files 2013-11-25 02:12:58 +01:00
.gitmodules gitmodules: Fix 3rdparty updates 2013-06-28 00:56:43 +02:00
.gitreview add .gitreview 2012-11-01 23:13:39 +01:00
COPYING update license template. 2006-08-12 22:03:36 +00:00
Makefile arch/x86/Makefile.inc: Pass $(AS) and $(CPP) to SeaBIOS 2013-10-17 01:59:50 +02:00
Makefile.inc sandybridge: Make build possible without descriptor.bin 2013-06-24 17:42:48 +02:00
README Update README with newer version of the text from the web page 2011-06-15 10:16:33 +02:00

README

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See http://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * http://www.coreboot.org/Supported_Motherboards
 * http://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * gcc / g++
 * make

Optional:

 * doxygen (for generating/viewing documentation)
 * iasl (for targets with ACPI support)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult http://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see http://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  http://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  http://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.