a46a712610
In the file `COPYING` in the coreboot repository and upstream [1]
just one space is used.
The following command was used to convert all files.
$ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/'
[1] http://www.gnu.org/licenses/gpl-2.0.txt
Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2490
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
77 lines
2.1 KiB
C
77 lines
2.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <arch/io.h>
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#include <boot/tables.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <device/pci_def.h>
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#include <NbPlatform.h>
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#include "chip.h"
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void set_pcie_dereset(void *nbconfig);
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void set_pcie_reset(void *nbconfig);
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/**
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*
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*/
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void set_pcie_reset(void *nbconfig)
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{
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}
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/**
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* Mainboard specific RD890 CIMx callback
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* Release Resets to PCIe Links
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* For Both SR56X0 chips, PCIE_RESET_GPIO1 to reset pcie
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*/
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void set_pcie_dereset(void *nbconfig)
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{
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//u32 nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0);
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u32 i;
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u32 val;
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u32 nb_addr;
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val = 0x00000007UL;
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AMD_NB_CONFIG_BLOCK *pConfig = (AMD_NB_CONFIG_BLOCK*)nbconfig;
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for (i = 0; i < MAX_NB_COUNT; i ++) {
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nb_addr = pConfig->Northbridges[i].NbPciAddress.AddressValue | NB_HTIU_INDEX;
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LibNbPciIndexRMW(nb_addr,
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NB_HTIU_REGA8,
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AccessS3SaveWidth32,
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~val,
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val,
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&(pConfig->Northbridges[i]));
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}
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}
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/*************************************************
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* enable the dedicated function in s8226 board.
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*************************************************/
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static void mainboard_enable(device_t dev)
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{
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printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
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}
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struct chip_operations mainboard_ops = {
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.enable_dev = mainboard_enable,
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};
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