bc134812c3
The common code gets moved to soc/amd/common/block/cpu/smm, since it is related to the CPU cores and soc/amd/common/block/smi is about the SMI/ SCI functionality in the FCH part. Also relocation_handler gets renamed to smm_relocation_handler to keep it clear what it does, since it got moved to another compilation unit. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I45224131dfd52247018c5ca19cb37c44062b03eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/50462 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
89 lines
2.1 KiB
C
89 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
|
|
|
|
#include <amdblocks/cpu.h>
|
|
#include <amdblocks/smm.h>
|
|
#include <cpu/cpu.h>
|
|
#include <cpu/x86/mp.h>
|
|
#include <cpu/x86/mtrr.h>
|
|
#include <cpu/x86/msr.h>
|
|
#include <cpu/x86/smm.h>
|
|
#include <cpu/x86/lapic.h>
|
|
#include <device/device.h>
|
|
#include <device/pci_ops.h>
|
|
#include <soc/pci_devs.h>
|
|
#include <soc/cpu.h>
|
|
#include <soc/reset.h>
|
|
#include <soc/smi.h>
|
|
#include <soc/iomap.h>
|
|
#include <console/console.h>
|
|
#include <cpu/amd/microcode.h>
|
|
|
|
/*
|
|
* MP and SMM loading initialization.
|
|
*/
|
|
|
|
/*
|
|
* Do essential initialization tasks before APs can be fired up -
|
|
*
|
|
* 1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This
|
|
* creates the MTRR solution that the APs will use. Otherwise APs will try to
|
|
* apply the incomplete solution as the BSP is calculating it.
|
|
*/
|
|
static void pre_mp_init(void)
|
|
{
|
|
x86_setup_mtrrs_with_detect_no_above_4gb();
|
|
x86_mtrr_check();
|
|
}
|
|
|
|
static void post_mp_init(void)
|
|
{
|
|
global_smi_enable();
|
|
apm_control(APM_CNT_SMMINFO);
|
|
}
|
|
|
|
static const struct mp_ops mp_ops = {
|
|
.pre_mp_init = pre_mp_init,
|
|
.get_cpu_count = get_cpu_count,
|
|
.get_smm_info = get_smm_info,
|
|
.relocation_handler = smm_relocation_handler,
|
|
.post_mp_init = post_mp_init,
|
|
};
|
|
|
|
void mp_init_cpus(struct bus *cpu_bus)
|
|
{
|
|
/* Clear for take-off */
|
|
if (mp_init_with_smm(cpu_bus, &mp_ops) < 0)
|
|
printk(BIOS_ERR, "MP initialization failure.\n");
|
|
|
|
/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
|
|
mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
|
|
|
|
set_warm_reset_flag();
|
|
}
|
|
|
|
static void model_17_init(struct device *dev)
|
|
{
|
|
check_mca();
|
|
setup_lapic();
|
|
set_cstate_io_addr();
|
|
|
|
amd_update_microcode_from_cbfs();
|
|
}
|
|
|
|
static struct device_operations cpu_dev_ops = {
|
|
.init = model_17_init,
|
|
};
|
|
|
|
static struct cpu_device_id cpu_table[] = {
|
|
{ X86_VENDOR_AMD, RAVEN1_B0_CPUID},
|
|
{ X86_VENDOR_AMD, PICASSO_B0_CPUID },
|
|
{ X86_VENDOR_AMD, PICASSO_B1_CPUID },
|
|
{ X86_VENDOR_AMD, RAVEN2_A0_CPUID },
|
|
{ X86_VENDOR_AMD, RAVEN2_A1_CPUID },
|
|
{ 0, 0 },
|
|
};
|
|
|
|
static const struct cpu_driver model_17 __cpu_driver = {
|
|
.ops = &cpu_dev_ops,
|
|
.id_table = cpu_table,
|
|
};
|