1c3b1112fa
On some devices it can happen that DisplayPort TX lanes do not work properly if the power gate setup is omitted. If that happens, DisplayPort training will fail and therefore DisplayPort channel will not work. Both ports are affected. It seems that not every CPU shows this effect and those that are affected tend to fail more often in a cold environment. With this fix a board that originally shows this failure was running for over 1000 power cycles without issues. Change-Id: Ia266674490a1bee63a85b38d1dc949dcdf683cbc Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/13743 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
63 lines
1.9 KiB
Makefile
63 lines
1.9 KiB
Makefile
#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2010 Google Inc.
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# Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
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# Copyright (C) 2016 Siemens AG
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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ifeq ($(CONFIG_SOC_INTEL_FSP_BAYTRAIL),y)
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subdirs-y += romstage
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subdirs-y += ../../../cpu/x86/lapic
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subdirs-y += ../../../cpu/x86/mtrr
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subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm
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subdirs-y += ../../../cpu/x86/tsc
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subdirs-y += ../../../cpu/x86/cache
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subdirs-y += ../../../cpu/intel/microcode
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subdirs-y += ../../../cpu/intel/turbo
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subdirs-y += ../../../lib/fsp
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subdirs-y += fsp
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ramstage-y += memmap.c
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romstage-y += memmap.c
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ramstage-y += tsc_freq.c
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romstage-y += tsc_freq.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
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ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c
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ramstage-y += spi.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += spi.c
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ramstage-y += chip.c
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ramstage-y += iosf.c
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romstage-y += iosf.c
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ramstage-y += northcluster.c
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ramstage-y += ramstage.c
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ramstage-y += gpio.c
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romstage-y += gpio.c
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ramstage-y += pmutil.c
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ramstage-y += southcluster.c
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romstage-y += reset.c
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ramstage-y += reset.c
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ramstage-y += cpu.c
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ramstage-y += acpi.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c
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ramstage-y += placeholders.c
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ramstage-y += i2c.c
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ramstage-(CONFIG_FSP_BAYTRAIL_GFX_INIT) += gfx.c
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CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/include
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CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp
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endif
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