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Srinidhi N Kaushik 083379d0f8 vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v2527 
Update FSP headers for Tiger Lake platform generated based FSP
version 2527. Which includes below additional UPDs:

FSPM:
 - PchTraceHubMode
 - CpuTraceHubMode
 - CpuPcieRpEnableMask
FSPS:
 - D3HotEnable
 - D3ColdEnable
 - RtcMemoryLock
 - PchLockDownGlobalSmi
 - PchLockDownBiosInterface
 - PchUnlockGpioPads
 - CpuMpPpi
 - ThcPort0Assignment
 - ThcPort1Assignment

BUG=b:150357377
BRANCH=none
TEST=build and boot ripto/volteer

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I0cdce28b01f291dbb02a01ded7629e94c77b7e47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40026
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-11 20:28:26 +00:00
..
edk2 Make common macros double-evaluation safe 2019-04-04 19:38:31 +00:00
fsp vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v2527 2020-04-11 20:28:26 +00:00
Kconfig src (minus soc and mainboard): Remove copyright notices 2020-03-17 18:26:34 +00:00
Makefile.inc src (minus soc and mainboard): Remove copyright notices 2020-03-17 18:26:34 +00:00