Srinidhi N Kaushik d801b1feb8 soc/intel/tigerlake: Update fsp_params for TGL ... Add initial fsp upd settings for TGL, both romstage and ramstage upd's to support basic build and boot of TGL RVP. - Add Silicon upd settings which includes * Serial IO/UART settings * Graphics settings * USB2/USB3 settings - Add Romstage upd settings which includes * Pcie Root port settings * IGD initialization * Hyper Threading settings * SMBus controller settings * Debug probe settings BUG=none BRANCH=none TEST=Build and boot Tigerlake rvp board Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I16df66451fd3a681df1222d283d97dd6bdaff0e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37960 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-01-22 15:43:12 +00:00
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amd	{soc,southbridge}/*/*/acpi: Add possibility to disable S4	2020-01-22 15:41:02 +00:00
cavium	soc/{amd,cavium,mediatek,sifive}: Remove unused <stdlib.h>	2019-12-19 05:38:43 +00:00
intel	soc/intel/tigerlake: Update fsp_params for TGL	2020-01-22 15:43:12 +00:00
mediatek	soc/mediatek/mt8183: Restore vcore after DRAM calibration	2020-01-10 14:47:59 +00:00
nvidia	src/soc/nvidia: Remove unused <stdlib.h>	2019-12-19 04:06:52 +00:00
qualcomm	soc/qualcomm/qcs405: Remove unused QCS405_BLSP_SPI	2020-01-02 14:31:31 +00:00
rockchip	src: Replace min/max() with MIN/MAX()	2019-12-20 17:49:29 +00:00
samsung	src/soc/samsung: Remove unused <stdlib.h>	2019-12-19 05:39:09 +00:00
sifive	src: Replace min/max() with MIN/MAX()	2019-12-20 17:49:29 +00:00
ucb	mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike.	2019-12-06 15:09:48 +00:00