a73b93157f
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
241 lines
7 KiB
C
241 lines
7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/pci.h>
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#include <console/console.h>
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#include <soc/gpio.h>
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#include <soc/pmc.h>
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#include <soc/smm.h>
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/* GPIO-to-Pad LUTs */
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static const u8 gpncore_gpio_to_pad[GPNCORE_COUNT] =
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{ 19, 18, 17, 20, 21, 22, 24, 25, /* [ 0: 7] */
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23, 16, 14, 15, 12, 26, 27, 1, /* [ 8:15] */
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4, 8, 11, 0, 3, 6, 10, 13, /* [16:23] */
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2, 5, 9 }; /* [24:26] */
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static const u8 gpscore_gpio_to_pad[GPSCORE_COUNT] =
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{ 85, 89, 93, 96, 99, 102, 98, 101, /* [ 0: 7] */
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34, 37, 36, 38, 39, 35, 40, 84, /* [ 8: 15] */
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62, 61, 64, 59, 54, 56, 60, 55, /* [16: 23] */
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63, 57, 51, 50, 53, 47, 52, 49, /* [24: 31] */
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48, 43, 46, 41, 45, 42, 58, 44, /* [32: 39] */
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95, 105, 70, 68, 67, 66, 69, 71, /* [40: 47] */
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65, 72, 86, 90, 88, 92, 103, 77, /* [48: 55] */
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79, 83, 78, 81, 80, 82, 13, 12, /* [56: 63] */
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15, 14, 17, 18, 19, 16, 2, 1, /* [64: 71] */
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0, 4, 6, 7, 9, 8, 33, 32, /* [72: 79] */
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31, 30, 29, 27, 25, 28, 26, 23, /* [80: 87] */
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21, 20, 24, 22, 5, 3, 10, 11, /* [88: 95] */
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106, 87, 91, 104, 97, 100 }; /* [96:101] */
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static const u8 gpssus_gpio_to_pad[GPSSUS_COUNT] =
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{ 29, 33, 30, 31, 32, 34, 36, 35, /* [ 0: 7] */
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38, 37, 18, 7, 11, 20, 17, 1, /* [ 8:15] */
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8, 10, 19, 12, 0, 2, 23, 39, /* [16:23] */
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28, 27, 22, 21, 24, 25, 26, 51, /* [24:31] */
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56, 54, 49, 55, 48, 57, 50, 58, /* [32:39] */
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52, 53, 59, 40 }; /* [40:43] */
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/* GPIO bank descriptions */
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static const struct gpio_bank gpncore_bank = {
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.gpio_count = GPNCORE_COUNT,
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.gpio_to_pad = gpncore_gpio_to_pad,
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.legacy_base = GP_LEGACY_BASE_NONE,
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.pad_base = GPNCORE_PAD_BASE,
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.has_wake_en = 0,
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.gpio_f1_range_start = GPNCORE_GPIO_F1_RANGE_START,
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.gpio_f1_range_end = GPNCORE_GPIO_F1_RANGE_END,
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};
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static const struct gpio_bank gpscore_bank = {
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.gpio_count = GPSCORE_COUNT,
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.gpio_to_pad = gpscore_gpio_to_pad,
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.legacy_base = GPSCORE_LEGACY_BASE,
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.pad_base = GPSCORE_PAD_BASE,
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.has_wake_en = 0,
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.gpio_f1_range_start = GPSCORE_GPIO_F1_RANGE_START,
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.gpio_f1_range_end = GPSCORE_GPIO_F1_RANGE_END,
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};
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static const struct gpio_bank gpssus_bank = {
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.gpio_count = GPSSUS_COUNT,
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.gpio_to_pad = gpssus_gpio_to_pad,
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.legacy_base = GPSSUS_LEGACY_BASE,
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.pad_base = GPSSUS_PAD_BASE,
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.has_wake_en = 1,
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.gpio_f1_range_start = GPSSUS_GPIO_F1_RANGE_START,
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.gpio_f1_range_end = GPSSUS_GPIO_F1_RANGE_END,
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};
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static void setup_gpios(const struct soc_gpio_map *gpios,
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const struct gpio_bank *bank)
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{
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const struct soc_gpio_map *config;
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int gpio = 0;
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u32 reg, pad_conf0;
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u8 set, bit;
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u32 use_sel[4] = {0};
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u32 io_sel[4] = {0};
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u32 gp_lvl[4] = {0};
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u32 tpe[4] = {0};
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u32 tne[4] = {0};
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u32 wake_en[4] = {0};
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if (!gpios)
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return;
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for (config = gpios; config->pad_conf0 != GPIO_LIST_END;
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config++, gpio++) {
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if (gpio > bank->gpio_count)
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break;
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set = gpio >> 5;
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bit = gpio % 32;
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if (bank->legacy_base != GP_LEGACY_BASE_NONE) {
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/* Legacy IO configuration */
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use_sel[set] |= config->use_sel << bit;
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io_sel[set] |= config->io_sel << bit;
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gp_lvl[set] |= config->gp_lvl << bit;
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tpe[set] |= config->tpe << bit;
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tne[set] |= config->tne << bit;
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/* Some banks do not have wake_en ability */
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if (bank->has_wake_en)
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wake_en[set] |= config->wake_en << bit;
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}
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/* Pad configuration registers */
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reg = bank->pad_base + 16 * bank->gpio_to_pad[gpio];
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/* Add correct func to GPIO pad config */
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pad_conf0 = config->pad_conf0;
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if (config->is_gpio)
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{
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if (gpio >= bank->gpio_f1_range_start &&
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gpio <= bank->gpio_f1_range_end)
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pad_conf0 |= PAD_FUNC1;
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else
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pad_conf0 |= PAD_FUNC0;
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}
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#ifdef GPIO_DEBUG
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printk(BIOS_DEBUG, "Write Pad: Base(%x) - %x %x %x\n",
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reg, pad_conf0, config->pad_conf1, config->pad_val);
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#endif
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write32((u32 *)(reg + PAD_CONF0_REG), pad_conf0);
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write32((u32 *)(reg + PAD_CONF1_REG), config->pad_conf1);
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write32((u32 *)(reg + PAD_VAL_REG), config->pad_val);
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}
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if (bank->legacy_base != GP_LEGACY_BASE_NONE)
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for (set = 0; set <= (bank->gpio_count - 1) / 32; ++set) {
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reg = bank->legacy_base + 0x20 * set;
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#ifdef GPIO_DEBUG
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printk(BIOS_DEBUG,
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"Write GPIO: Reg(%x) - %x %x %x %x %x\n",
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reg, use_sel[set], io_sel[set], gp_lvl[set],
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tpe[set], tne[set]);
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#endif
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outl(use_sel[set], reg + LEGACY_USE_SEL_REG);
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outl(io_sel[set], reg + LEGACY_IO_SEL_REG);
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outl(gp_lvl[set], reg + LEGACY_GP_LVL_REG);
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outl(tpe[set], reg + LEGACY_TPE_REG);
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outl(tne[set], reg + LEGACY_TNE_REG);
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/* TS registers are WOC */
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outl(0, reg + LEGACY_TS_REG);
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if (bank->has_wake_en)
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outl(wake_en[set], reg + LEGACY_WAKE_EN_REG);
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}
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}
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static void setup_gpio_route(const struct soc_gpio_map *sus,
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const struct soc_gpio_map *core)
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{
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uint32_t route_reg = 0;
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int i;
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for (i = 0; i < 8; i++) {
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/* SMI takes precedence and wake_en implies SCI. */
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if (sus[i].smi) {
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route_reg |= ROUTE_SMI << (2 * i);
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} else if (sus[i].sci) {
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route_reg |= ROUTE_SCI << (2 * i);
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}
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if (core[i].smi) {
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route_reg |= ROUTE_SMI << (2 * (i + 8));
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} else if (core[i].sci) {
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route_reg |= ROUTE_SCI << (2 * (i + 8));
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}
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}
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southcluster_smm_save_param(SMM_SAVE_PARAM_GPIO_ROUTE, route_reg);
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}
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static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS],
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const struct gpio_bank *bank)
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{
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u32 *reg = (u32 *)(bank->pad_base + PAD_BASE_DIRQ_OFFSET);
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u32 val;
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int i;
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/* Write all four DIRQ registers */
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for (i=0; i<4; ++i) {
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val = dirq[i * 4 + 3] << 24 | dirq[i * 4 + 2] << 16 |
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dirq[i * 4 + 1] << 8 | dirq[i * 4];
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write32(reg + i, val);
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#ifdef GPIO_DEBUG
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printk(BIOS_DEBUG, "Write DIRQ reg(%x) - %x\n",
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reg + i, val);
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#endif
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}
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}
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void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap)
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{
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if (config) {
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setup_gpios(config->ncore, &gpncore_bank);
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setup_gpios(config->score, &gpscore_bank);
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setup_gpios(config->ssus, &gpssus_bank);
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setup_gpio_route(config->ssus, config->score);
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if (config->core_dirq)
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setup_dirqs(*config->core_dirq, &gpscore_bank);
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if (config->sus_dirq)
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setup_dirqs(*config->sus_dirq, &gpssus_bank);
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}
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/* Set on die termination feature with pull up value and
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* drive the pad high for TAP_TDO and TAP_TMS
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*/
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if (!enable_xdp_tap) {
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printk(BIOS_DEBUG, "Tri-state TDO and TMS\n");
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write32((u32 *)(GPSSUS_PAD_BASE + 0x2fc), 0xc);
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write32((u32 *)(GPSSUS_PAD_BASE + 0x2cc), 0xc);
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}
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}
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struct soc_gpio_config* __attribute__((weak)) mainboard_get_gpios(void)
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{
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printk(BIOS_DEBUG, "Default/empty GPIO config\n");
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return NULL;
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}
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