dec279fa30
The code can run on the Mahogany board, which is one of sample boards made by AMD. Its major features are: CPU (only K8 system): * AMD AM2+ * AMD Athlon 64 x2 * AMD Athlon 64 FX * AMD Athlon 64 * AMD Sempron CPUs System Chipset: * RS780E * SB700 On Board Chipset: * BIOS - SPI * Azalia CODEC - Realtek ALC888 * LPC SuperIO - ITE8718F(GX). * LAN - REALTEK 8111C * TPM - SLB9635TT1.2 Main Memory: * DDR II * 4 (Max 4GB) Expansion Slots: * PCI Express X16 slot*2 (PCI-E X8 Bus) * PCI Express X4 Slot*1 Intersil PWM: * Controller - Intersil 6323 2. The ACPI feature is already added. I suggest that firstly we can test the board without the ACPI by setting the HAVE_ACPI_TABLE as 0. With Rev F processor, the HT link can only work in HT1, whose max frequency is 1GHz. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5220 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
161 lines
2.9 KiB
Text
161 lines
2.9 KiB
Text
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* simple name description */
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/*
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DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
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)
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{
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#include "usb.asl"
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}
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*/
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Method(UCOC, 0) {
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Sleep(20)
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Store(0x13,CMTI)
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Store(0,GPSL)
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}
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/* USB Port 0 overcurrent uses Gpm 0 */
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If(LLessEqual(UOM0,9)) {
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Scope (\_GPE) {
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Method (_L13) {
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UCOC()
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if(LEqual(GPB0,PLC0)) {
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Not(PLC0,PLC0)
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Store(PLC0, \_SB.PT0D)
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}
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}
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}
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}
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/* USB Port 1 overcurrent uses Gpm 1 */
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If (LLessEqual(UOM1,9)) {
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Scope (\_GPE) {
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Method (_L14) {
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UCOC()
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if (LEqual(GPB1,PLC1)) {
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Not(PLC1,PLC1)
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Store(PLC1, \_SB.PT1D)
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}
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}
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}
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}
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/* USB Port 2 overcurrent uses Gpm 2 */
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If (LLessEqual(UOM2,9)) {
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Scope (\_GPE) {
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Method (_L15) {
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UCOC()
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if (LEqual(GPB2,PLC2)) {
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Not(PLC2,PLC2)
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Store(PLC2, \_SB.PT2D)
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}
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}
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}
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}
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/* USB Port 3 overcurrent uses Gpm 3 */
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If (LLessEqual(UOM3,9)) {
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Scope (\_GPE) {
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Method (_L16) {
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UCOC()
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if (LEqual(GPB3,PLC3)) {
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Not(PLC3,PLC3)
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Store(PLC3, \_SB.PT3D)
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}
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}
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}
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}
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/* USB Port 4 overcurrent uses Gpm 4 */
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If (LLessEqual(UOM4,9)) {
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Scope (\_GPE) {
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Method (_L19) {
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UCOC()
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if (LEqual(GPB4,PLC4)) {
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Not(PLC4,PLC4)
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Store(PLC4, \_SB.PT4D)
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}
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}
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}
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}
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/* USB Port 5 overcurrent uses Gpm 5 */
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If (LLessEqual(UOM5,9)) {
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Scope (\_GPE) {
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Method (_L1A) {
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UCOC()
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if (LEqual(GPB5,PLC5)) {
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Not(PLC5,PLC5)
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Store(PLC5, \_SB.PT5D)
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}
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}
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}
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}
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/* USB Port 6 overcurrent uses Gpm 6 */
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If (LLessEqual(UOM6,9)) {
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Scope (\_GPE) {
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/* Method (_L1C) { */
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Method (_L06) {
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UCOC()
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if (LEqual(GPB6,PLC6)) {
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Not(PLC6,PLC6)
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Store(PLC6, \_SB.PT6D)
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}
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}
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}
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}
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/* USB Port 7 overcurrent uses Gpm 7 */
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If (LLessEqual(UOM7,9)) {
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Scope (\_GPE) {
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/* Method (_L1D) { */
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Method (_L07) {
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UCOC()
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if (LEqual(GPB7,PLC7)) {
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Not(PLC7,PLC7)
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Store(PLC7, \_SB.PT7D)
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}
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}
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}
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}
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/* USB Port 8 overcurrent uses Gpm 8 */
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If (LLessEqual(UOM8,9)) {
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Scope (\_GPE) {
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Method (_L17) {
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if (LEqual(G8IS,PLC8)) {
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Not(PLC8,PLC8)
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Store(PLC8, \_SB.PT8D)
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}
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}
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}
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}
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/* USB Port 9 overcurrent uses Gpm 9 */
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If (LLessEqual(UOM9,9)) {
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Scope (\_GPE) {
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Method (_L0E) {
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if (LEqual(G9IS,0)) {
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Store(1,\_SB.PT9D)
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}
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}
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}
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}
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