No description
da3a146cae
The configuration of SPSR bits that mask processor exceptions is kinda oddly hidden as an implict part of the transition() function right now. It would be odd but not impossible for programs to want to be entered with enabled exceptions, so let's move these bits to be explicitly set by the caller like the rest of SPSR instead. Also clear up some macro names. The SPSR[I] bit is currently defined as SPSR_IRQ_ENABLE, which is particularly unfortunate since that bit actually *disables* (masks) interrupts. The fact that there is an additional SPSR_IRQ_MASK definition with the same value but a different purpose doesn't really help. There's rarely a point to have all three of xxx_SHIFT, xxx_MASK and xxx_VALUE macros for single-bit fields, so simplify this to a single definition per bit. (Other macros in lib_helpers.h should probably also be overhauled to conform, but I want to wait and see how many of them really stay relevant after upcoming changes first.) BRANCH=None BUG=None TEST=None Change-Id: Id126f70d365467e43b7f493c341542247e5026d2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 715600c83aef9794d1674e8c3b62469bdc57f297 Original-Change-Id: I3edc4ee276feb8610a636ec7b4175706505d58bd Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/270785 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10250 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> |
||
|---|---|---|
| 3rdparty | ||
| Documentation | ||
| payloads | ||
| src | ||
| util | ||
| .gitignore | ||
| .gitmodules | ||
| .gitreview | ||
| COPYING | ||
| MAINTAINERS | ||
| Makefile | ||
| Makefile.inc | ||
| README | ||
| toolchain.inc | ||
------------------------------------------------------------------------------- coreboot README ------------------------------------------------------------------------------- coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload. With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required. coreboot was formerly known as LinuxBIOS. Payloads -------- After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot. See http://www.coreboot.org/Payloads for a list of supported payloads. Supported Hardware ------------------ coreboot supports a wide range of chipsets, devices, and mainboards. For details please consult: * http://www.coreboot.org/Supported_Motherboards * http://www.coreboot.org/Supported_Chipsets_and_Devices Build Requirements ------------------ * gcc / g++ * make Optional: * doxygen (for generating/viewing documentation) * iasl (for targets with ACPI support) * gdb (for better debugging facilities on some targets) * ncurses (for 'make menuconfig') * flex and bison (for regenerating parsers) Building coreboot ----------------- Please consult http://www.coreboot.org/Build_HOWTO for details. Testing coreboot Without Modifying Your Hardware ------------------------------------------------ If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU. Please see http://www.coreboot.org/QEMU for details. Website and Mailing List ------------------------ Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website: http://www.coreboot.org You can contact us directly on the coreboot mailing list: http://www.coreboot.org/Mailinglist Copyright and License --------------------- The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details. coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details. This makes the resulting coreboot images licensed under the GPL, version 2.