Christian Walter da60958ae3 superio/aspeed/ast2400: Fix Register Offset ... According to the specification the register offset must be 0x71 instead of 0x70. Change-Id: Icf69ffc701a42a31a4545ce53c13e2c2554863e1 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>		2020-01-26 18:23:33 +00:00
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acpi	src: Capitalize Super I/O	2019-10-07 19:18:36 +00:00
aspeed	superio/aspeed/ast2400: Fix Register Offset	2020-01-26 18:23:33 +00:00
common	acpi: Be more ACPI compliant when generating _UID	2020-01-09 14:22:51 +00:00
fintek	mb/msi/ms7721: Don't rewrite pnp_{enter,exit}_conf_state function	2019-12-15 11:54:54 +00:00
ite	drivers/pc80/rtc: Separate {get|set}_option() prototypes	2020-01-09 14:37:33 +00:00
nsc	src: Remove some romcc workarounds	2019-12-31 15:22:43 +00:00
nuvoton	superio/nuvoton/nct5104d: Add virtual LDN for simple GPIO IO control	2020-01-20 11:09:57 +00:00
renesas	superio: Use 'include <stdlib.h>' when appropriate	2019-10-20 15:55:25 +00:00
serverengines	superio/serverengines/pilot: Fix typo	2019-12-05 15:29:09 +00:00
smsc	superio/smsc/lpc47m10x: Expose pnp_enter/exit_conf_state	2019-12-20 17:51:10 +00:00
winbond	drivers/pc80/rtc: Separate {get|set}_option() prototypes	2020-01-09 14:37:33 +00:00
Makefile.inc	superio: Add ASpeed AST2400	2019-05-24 07:22:23 +00:00