Ryan Chuang da63f09b80 mb/google/cherry: Initialize DPM in romstage ... Add initialization of DPM drvier used by DRAM calibration test. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I8bd10864267dfa4db8528d40483eccee2d05c1d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>		2021-06-24 03:14:28 +00:00
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acpi	ACPI: Refactor use of global and device NVS	2021-06-14 19:45:56 +00:00
arch	arch/x86/include/arch/smp/mpspec: improve mp_bustype enum definition	2021-06-18 16:02:09 +00:00
commonlib	nvs: Add Chrome OS NVS (CNVS) information to coreboot tables	2021-06-18 18:38:14 +00:00
console	src/console/init.c: Make get_log_level static inline again	2021-06-15 16:12:52 +00:00
cpu	soc/intel/common/block/smm: Add `mainboard_smi_finalize`	2021-06-19 00:06:41 +00:00
device	device: Add helper function devfn_disable()	2021-06-17 06:48:45 +00:00
drivers	drivers/intel/mipi_camera: Change type for gpio_num to uint16_t	2021-06-21 05:34:58 +00:00
ec	ec/google/wilco: Fix comment about enclosure type	2021-06-21 05:43:52 +00:00
include	soc/intel/car: Add support for bootguard CAR	2021-06-22 13:15:09 +00:00
lib	nvs: Add Chrome OS NVS (CNVS) information to coreboot tables	2021-06-18 18:38:14 +00:00
mainboard	mb/google/cherry: Initialize DPM in romstage	2021-06-24 03:14:28 +00:00
northbridge	nb/intel/haswell/pcie.c: Avoid needless death	2021-06-22 04:47:20 +00:00
security	security/intel: Add option to enable SMM flash access only	2021-06-21 08:11:11 +00:00
soc	soc/mediatek/mt8195: Support 4 channel DRAM in DPM init flow	2021-06-24 03:13:53 +00:00
southbridge	security/intel: Add option to enable SMM flash access only	2021-06-21 08:11:11 +00:00
superio	src: Retype option API to use unsigned integers	2021-05-06 14:48:15 +00:00
vendorcode	vc/amd/fsp/cezanne/FspmUpd: add hda_enable UPD	2021-06-21 15:15:17 +00:00
Kconfig	option: Allow mainboards to implement the API	2021-05-28 11:37:25 +00:00