coreboot-kgpe-d16/src/soc/intel/elkhartlake/sd.c
Tan, Lean Sheng 05dfe3177d soc/intel/elkhartlake: Do initial SoC commit till ramstage
Clone entirely from Jasperlake

List of changes on top off initial jasperlake clone
1. Replace "Jasperlake" with "Elkhartlake"
2. Replace "jsl" with "ehl"
3. Replace "jsp" with "mcc"
4. Rename structure based on Jasperlake with Elkhartlake
5. Clean up upd override in fsp_params.c will be added later
6. Sort #include files alphabetically as per comment
7. Remove doc details from espi.c until it is ready
8. Remove pch_isclk & camera clocks related codes
9. Add new #define NMI_STS_CNT & NMI_EN as per comment

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I372b0bb5912e013445ed8df7c58d0a9ee9a7cf35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-09-08 05:29:37 +00:00

24 lines
623 B
C

/* SPDX-License-Identifier: GPL-2.0-only */
#include <intelblocks/sd.h>
#include <soc/soc_chip.h>
int sd_fill_soc_gpio_info(struct acpi_gpio *gpio, const struct device *dev)
{
config_t *config = config_of(dev);
if (!config->sdcard_cd_gpio)
return -1;
gpio->type = ACPI_GPIO_TYPE_INTERRUPT;
gpio->pull = ACPI_GPIO_PULL_NONE;
gpio->irq.mode = ACPI_IRQ_EDGE_TRIGGERED;
gpio->irq.polarity = ACPI_IRQ_ACTIVE_BOTH;
gpio->irq.shared = ACPI_IRQ_SHARED;
gpio->irq.wake = ACPI_IRQ_WAKE;
gpio->interrupt_debounce_timeout = 10000; /* 100ms */
gpio->pin_count = 1;
gpio->pins[0] = config->sdcard_cd_gpio;
return 0;
}