Subrata Banik e9b937352e apollolake boards: Enable CSE in devicetree ... Enable CSE PCI device Bus 0: Device 0x0f: Function 0x00 to let Intel common cse block code can use this device. Calling me_read_config32(offset) function from ramstage: Without this CL : HECI: Global Reset(Type:1) Command BUG: me_read_config32 requests hidden 00:0f.0 PCI: dev is NULL! With this CL : HECI: Global Reset(Type:1) Command HECI: Global Reset success! Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I97d221ae52b4b03ecd859d708847ad77fe4bf465 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>		2020-09-19 06:37:24 +00:00
..
mc_apl1	apollolake boards: Enable CSE in devicetree	2020-09-19 06:37:24 +00:00
Kconfig	mb/*/Kconfig: Factor out MAINBOARD_VENDOR	2020-03-03 10:15:22 +00:00
Kconfig.name	kconfig: automatically include mainboards	2015-04-18 08:31:08 +02:00