3e706b63c0
sb800 pci bridge SHOULD enabled by default according to the chipset document, but actually not enabled on some mainboard. enable sb800 pci bridge when told to enable in devicetree.cb. tested on ibase persimmon mainboard. Change-Id: I42075907b4a003b2e58e5b19635a2e1b3fe094c3 Signed-off-by: Kerry She <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/63 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
124 lines
6.1 KiB
Text
124 lines
6.1 KiB
Text
# sample config for advansus/A785E-I
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chip northbridge/amd/amdfam10/root_complex
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device lapic_cluster 0 on
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chip cpu/amd/socket_ASB2 #L1 and DDR3
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device lapic 0 on end
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end
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end
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device pci_domain 0 on
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subsystemid 0x1612 0x3060 inherit #TODO: Set the correctly subsystem id.
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chip northbridge/amd/amdfam10
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device pci 18.0 on # northbridge
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chip southbridge/amd/rs780
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device pci 0.0 on end # HT 0x9600
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device pci 1.0 on end # Internal Graphics P2P bridge 0x9712
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device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
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device pci 3.0 off end # PCIE P2P bridge 0x960b
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device pci 4.0 on end # PCIE P2P bridge 0x9604 wireless
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device pci 5.0 off end # PCIE P2P bridge 0x9605
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device pci 6.0 off end # PCIE P2P bridge 0x9606
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device pci 7.0 off end # PCIE P2P bridge 0x9607
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device pci 8.0 off end # NB/SB Link P2P bridge
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device pci 9.0 on end # Ethernet
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device pci a.0 on end # Ethernet
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register "gppsb_configuration" = "4" # Configuration E
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register "gpp_configuration" = "3" # Configuration D
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register "port_enable" = "0x6f6"
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register "gfx_dev2_dev3" = "0"
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register "gfx_dual_slot" = "0"
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register "gfx_lane_reversal" = "0"
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register "gfx_compliance" = "0"
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register "gfx_reconfiguration" = "1"
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register "gfx_link_width" = "0"
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register "gfx_tmds" = "1"
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register "gfx_pcie_config" = "3" # 1x8 GFX on Lanes 8-15
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register "gfx_ddi_config" = "1" # Lanes 0-3 DDI_SL
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end
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chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pci bus
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device pci 11.0 on end # SATA
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device pci 12.0 on end # USB
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device pci 12.2 on end # USB
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device pci 13.0 on end # USB
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device pci 13.2 on end # USB
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device pci 14.0 on # SM
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chip drivers/generic/generic #dimm 0-0-0
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device i2c 50 on end
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end
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chip drivers/generic/generic #dimm 0-0-1
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device i2c 51 on end
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end
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chip drivers/generic/generic #dimm 0-1-0
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device i2c 52 on end
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end
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chip drivers/generic/generic #dimm 0-1-1
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device i2c 53 on end
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end
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end # SM
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device pci 14.1 on end # IDE 0x439c
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device pci 14.2 on end # HDA 0x4383
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device pci 14.3 on
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chip superio/winbond/w83627hf
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device pnp 2e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 off # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.2 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 on # Com2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x72 = 12
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end
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device pnp 2e.6 off # SFI
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io 0x62 = 0x100
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end
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device pnp 2e.7 off # GPIO_GAME_MIDI
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io 0x60 = 0x220
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io 0x62 = 0x300
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irq 0x70 = 9
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end
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device pnp 2e.8 off end # WDTO_PLED
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device pnp 2e.9 off end # GPIO_SUSLED
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device pnp 2e.a off end # ACPI
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device pnp 2e.b on # HW Monitor
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io 0x60 = 0x290
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irq 0x70 = 5
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end
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end #superio/winbond/w83627hf
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end # LPC 0x439d
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device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
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device pci 14.5 on end # USB 2
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device pci 14.6 off end # Gec
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device pci 15.0 on end # PCIe 0
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device pci 15.1 on end # PCIe 1
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device pci 15.2 on end # PCIe 2
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device pci 15.3 on end # PCIe 3
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device pci 16.0 on end # USB
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device pci 16.2 on end # USB
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#register "gpp_configuration" = "0" #4:0:0:0
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#register "gpp_configuration" = "2" #2:2:0:0
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#register "gpp_configuration" = "3" #2:1:1:0
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register "gpp_configuration" = "4" #1:1:1:1
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register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
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end #southbridge/amd/cimx/sb800
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end # device pci 18.0
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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device pci 18.4 on end
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end
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end #pci_domain
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end
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