Angel Pons dca3cb572b nb/intel/sandybridge: Limit SRT to Ivy Bridge and slow RAM ... Reference code never enables SRT for Sandy Bridge, and only enables it for Ivy Bridge when the memory frequency is at most 1066 MHz. Tested on Asus P8H61-M PRO, still boots. Change-Id: I50527f311340584cf8290de2114ec2694cca3a83 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>		2020-11-19 23:03:38 +00:00
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e7505	src/northbridge: Drop unneeded empty lines	2020-09-21 16:32:10 +00:00
gm45	nb/intel/gm45: Clean up header handling	2020-10-24 20:42:32 +00:00
haswell	mrc_cache: Move code for triggering memory training into mrc_cache	2020-11-13 22:57:50 +00:00
i440bx	nb/intel/i440bx: Make ROM area unavailable for MMIO	2020-08-04 07:14:43 +00:00
i945	src: Include <arch/io.h> when appropriate	2020-10-26 06:44:40 +00:00
ironlake	src: Include <arch/io.h> when appropriate	2020-10-26 06:44:40 +00:00
pineview	nb/intel/pineview: Fix clearing memory	2020-11-09 07:28:01 +00:00
sandybridge	nb/intel/sandybridge: Limit SRT to Ivy Bridge and slow RAM	2020-11-19 23:03:38 +00:00
x4x	nb/intel/x4x: Place raminit definitions in raminit.h	2020-10-14 09:19:22 +00:00