265 lines
7.0 KiB
C
265 lines
7.0 KiB
C
/*
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* This file is part of the coreboot project.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cbfs.h>
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#include <console/console.h>
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#include <spd_bin.h>
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#include <string.h>
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#include <device/dram/ddr3.h>
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void dump_spd_info(struct spd_block *blk)
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{
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u8 i;
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for (i = 0; i < CONFIG_DIMM_MAX; i++)
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if (blk->spd_array[i] != NULL && blk->spd_array[i][0] != 0) {
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printk(BIOS_DEBUG, "SPD @ 0x%02X\n", blk->addr_map[i]);
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print_spd_info(blk->spd_array[i]);
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}
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}
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static bool use_ddr4_params(int dram_type)
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{
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switch (dram_type) {
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case SPD_DRAM_DDR3:
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case SPD_DRAM_LPDDR3_INTEL:
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return false;
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/* Below DDR type share the same attributes */
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case SPD_DRAM_LPDDR3_JEDEC:
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case SPD_DRAM_DDR4:
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case SPD_DRAM_LPDDR4:
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case SPD_DRAM_LPDDR4X:
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return true;
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default:
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printk(BIOS_ERR, "Defaulting to using DDR4 params. Please add dram_type check for %d to %s\n",
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dram_type, __func__);
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return true;
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}
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}
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static const char *spd_get_module_type_string(int dram_type)
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{
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switch (dram_type) {
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case SPD_DRAM_DDR3:
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return "DDR3";
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case SPD_DRAM_LPDDR3_INTEL:
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case SPD_DRAM_LPDDR3_JEDEC:
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return "LPDDR3";
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case SPD_DRAM_DDR4:
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return "DDR4";
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case SPD_DRAM_LPDDR4:
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return "LPDDR4";
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case SPD_DRAM_LPDDR4X:
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return "LPDDR4X";
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case SPD_DRAM_DDR5:
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return "DDR5";
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case SPD_DRAM_LPDDR5:
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return "LPDDR5";
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}
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return "UNKNOWN";
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}
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static int spd_get_banks(const uint8_t spd[], int dram_type)
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{
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static const int ddr3_banks[4] = { 8, 16, 32, 64 };
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static const int ddr4_banks[10] = { 4, 8, -1, -1, 8, 16, -1, -1, 16, 32 };
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int index = (spd[SPD_DENSITY_BANKS] >> 4) & 0xf;
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if (use_ddr4_params(dram_type)) {
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if (index >= ARRAY_SIZE(ddr4_banks))
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return -1;
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return ddr4_banks[index];
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} else {
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if (index >= ARRAY_SIZE(ddr3_banks))
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return -1;
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return ddr3_banks[index];
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}
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}
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static int spd_get_capmb(const uint8_t spd[])
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{
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static const int spd_capmb[13] = { 1, 2, 4, 8, 16, 32, 64,
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128, 48, 96, 12, 24, 72 };
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int index = spd[SPD_DENSITY_BANKS] & 0xf;
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if (index >= ARRAY_SIZE(spd_capmb))
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return -1;
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return spd_capmb[index] * 256;
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}
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static int spd_get_rows(const uint8_t spd[])
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{
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static const int spd_rows[7] = { 12, 13, 14, 15, 16, 17, 18 };
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int index = (spd[SPD_ADDRESSING] >> 3) & 7;
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if (index >= ARRAY_SIZE(spd_rows))
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return -1;
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return spd_rows[index];
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}
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static int spd_get_cols(const uint8_t spd[])
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{
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static const int spd_cols[4] = { 9, 10, 11, 12 };
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int index = spd[SPD_ADDRESSING] & 7;
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if (index >= ARRAY_SIZE(spd_cols))
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return -1;
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return spd_cols[index];
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}
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static int spd_get_ranks(const uint8_t spd[], int dram_type)
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{
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static const int spd_ranks[8] = { 1, 2, 3, 4, 5, 6, 7, 8 };
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int organ_offset = use_ddr4_params(dram_type) ? DDR4_ORGANIZATION
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: DDR3_ORGANIZATION;
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int index = (spd[organ_offset] >> 3) & 7;
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if (index >= ARRAY_SIZE(spd_ranks))
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return -1;
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return spd_ranks[index];
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}
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static int spd_get_devw(const uint8_t spd[], int dram_type)
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{
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static const int spd_devw[4] = { 4, 8, 16, 32 };
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int organ_offset = use_ddr4_params(dram_type) ? DDR4_ORGANIZATION
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: DDR3_ORGANIZATION;
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int index = spd[organ_offset] & 7;
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if (index >= ARRAY_SIZE(spd_devw))
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return -1;
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return spd_devw[index];
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}
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static int spd_get_busw(const uint8_t spd[], int dram_type)
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{
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static const int spd_busw[4] = { 8, 16, 32, 64 };
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int busw_offset = use_ddr4_params(dram_type) ? DDR4_BUS_DEV_WIDTH
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: DDR3_BUS_DEV_WIDTH;
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int index = spd[busw_offset] & 7;
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if (index >= ARRAY_SIZE(spd_busw))
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return -1;
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return spd_busw[index];
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}
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static void spd_get_name(const uint8_t spd[], char spd_name[], int dram_type)
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{
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switch (dram_type) {
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case SPD_DRAM_DDR3:
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memcpy(spd_name, &spd[DDR3_SPD_PART_OFF], DDR3_SPD_PART_LEN);
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spd_name[DDR3_SPD_PART_LEN] = 0;
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break;
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case SPD_DRAM_LPDDR3_INTEL:
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memcpy(spd_name, &spd[LPDDR3_SPD_PART_OFF],
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LPDDR3_SPD_PART_LEN);
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spd_name[LPDDR3_SPD_PART_LEN] = 0;
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break;
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/* LPDDR3, LPDDR4 and DDR4 have the same part number offset */
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case SPD_DRAM_LPDDR3_JEDEC:
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case SPD_DRAM_DDR4:
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case SPD_DRAM_LPDDR4:
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memcpy(spd_name, &spd[DDR4_SPD_PART_OFF], DDR4_SPD_PART_LEN);
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spd_name[DDR4_SPD_PART_LEN] = 0;
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break;
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default:
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break;
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}
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}
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void print_spd_info(uint8_t spd[])
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{
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char spd_name[DDR4_SPD_PART_LEN + 1] = { 0 };
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int type = spd[SPD_DRAM_TYPE];
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int banks = spd_get_banks(spd, type);
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int capmb = spd_get_capmb(spd);
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int rows = spd_get_rows(spd);
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int cols = spd_get_cols(spd);
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int ranks = spd_get_ranks(spd, type);
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int devw = spd_get_devw(spd, type);
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int busw = spd_get_busw(spd, type);
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/* Module type */
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printk(BIOS_INFO, "SPD: module type is %s\n",
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spd_get_module_type_string(type));
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/* Module Part Number */
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spd_get_name(spd, spd_name, type);
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printk(BIOS_INFO, "SPD: module part number is %s\n", spd_name);
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printk(BIOS_INFO,
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"SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n",
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banks, ranks, rows, cols, capmb);
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printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
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devw, busw);
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if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
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/* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
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printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
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capmb / 8 * busw / devw * ranks);
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}
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}
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int get_spd_cbfs_rdev(struct region_device *spd_rdev, u8 spd_index)
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{
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struct cbfsf fh;
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uint32_t cbfs_type = CBFS_TYPE_SPD;
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if (cbfs_boot_locate(&fh, "spd.bin", &cbfs_type) < 0)
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return -1;
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cbfs_file_data(spd_rdev, &fh);
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return rdev_chain(spd_rdev, spd_rdev, spd_index * CONFIG_DIMM_SPD_SIZE,
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CONFIG_DIMM_SPD_SIZE);
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}
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#if CONFIG_DIMM_SPD_SIZE == 128
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int read_ddr3_spd_from_cbfs(u8 *buf, int idx)
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{
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const int SPD_CRC_HI = 127;
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const int SPD_CRC_LO = 126;
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const char *spd_file;
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size_t spd_file_len = 0;
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size_t min_len = (idx + 1) * CONFIG_DIMM_SPD_SIZE;
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spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
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&spd_file_len);
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if (!spd_file)
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printk(BIOS_EMERG, "file [spd.bin] not found in CBFS");
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if (spd_file_len < min_len)
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printk(BIOS_EMERG, "Missing SPD data.");
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if (!spd_file || spd_file_len < min_len)
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return -1;
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memcpy(buf, spd_file + (idx * CONFIG_DIMM_SPD_SIZE),
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CONFIG_DIMM_SPD_SIZE);
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u16 crc = spd_ddr3_calc_crc(buf, CONFIG_DIMM_SPD_SIZE);
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if (((buf[SPD_CRC_LO] == 0) && (buf[SPD_CRC_HI] == 0))
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|| (buf[SPD_CRC_LO] != (crc & 0xff))
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|| (buf[SPD_CRC_HI] != (crc >> 8))) {
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printk(BIOS_WARNING,
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"SPD CRC %02x%02x is invalid, should be %04x\n",
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buf[SPD_CRC_HI], buf[SPD_CRC_LO], crc);
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buf[SPD_CRC_LO] = crc & 0xff;
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buf[SPD_CRC_HI] = crc >> 8;
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u16 i;
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printk(BIOS_WARNING, "\nDisplay the SPD");
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for (i = 0; i < CONFIG_DIMM_SPD_SIZE; i++) {
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if ((i % 16) == 0x00)
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printk(BIOS_WARNING, "\n%02x: ", i);
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printk(BIOS_WARNING, "%02x ", buf[i]);
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}
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printk(BIOS_WARNING, "\n");
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}
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return 0;
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}
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#endif
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