Martin Roth de49833268 soc/amd/picasso: Allow use of pre-built PSP verstage ... To use a signed PSP verstage, we're going to need to build it first, then sign and store the binary. This patch allows the stored (signed) verstage binary to be used. BUG=b:166108929 TEST=Build with existing verstage binary instead of re-building it. BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I5cbceca3b75f05c5460190b1c829d1ffaab2c736 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Eric Peers <epeers@google.com>		2020-09-03 16:30:25 +00:00
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amd	soc/amd/picasso: Allow use of pre-built PSP verstage	2020-09-03 16:30:25 +00:00
cavium	symbols: Change implementation details of DECLARE_OPTIONAL_REGION()	2020-08-27 22:11:17 +00:00
intel	soc/intel/tigerlake: Add mainboard hook for overriding SoC config	2020-09-02 10:37:20 +00:00
mediatek	{include,mb,soc,sb,vendorcode}: Make hexadecimal notation consistent	2020-09-01 03:06:04 +00:00
nvidia	{include,mb,soc,sb,vendorcode}: Make hexadecimal notation consistent	2020-09-01 03:06:04 +00:00
qualcomm	src: Drop redundant 'select BOOTBLOCK_CONSOLE'	2020-09-02 07:16:42 +00:00
rockchip	{include,mb,soc,sb,vendorcode}: Make hexadecimal notation consistent	2020-09-01 03:06:04 +00:00
samsung	src/soc/samsung/exynos{5250,s5420}: Add missing <{stddef,stdint}.h>	2020-07-29 09:34:55 +00:00
sifive	soc/sifive: Drop unneeded empty lines	2020-08-24 09:16:48 +00:00
ti	cpu/ti/am335x: Move from cpu to soc in tree	2020-08-19 07:17:37 +00:00
ucb