3fa1ad0d2c
Initialization for the Winbond W631GG6KB part using Synopsys DDR uMCTL and DDR Phy. This code adds a separate function for DDR3 initialization and moves all the necessary defines in a separate header file. The programming procedure that is executed at power up to bring up the uMCTL, PHY and memories into a state where reads and writes to the memory can be performed is the following: 1. uPCTL (Universal DDR protocol controller) initialization The timining registers TOGCNT1U, TINIT, TOGCNT100N and TRSTH needed for driving the memory power-up sequence are programmed as a function of the internal timers clock frequency. Organization (memory chip specific) values are set (column/bank/row address width and number of ranks), together with other static values (latency, timing, power up configuration). All these values are static, provided by the datasheet, being determined by the memory type, size and frequency. 2. PHY initialization The PHY is programmed with datasheet provided values, specifying the initialization values for it to send to the external memory (timing parameters). Also, delay lines (DLL) and strength of drive pads are calibrated (based on external conditions: temperature, voltage, noise) and locked. After that, the PHY goes through a trainig process (also dependent on the current conditions at boot time) to establish precise timing configuration between the DDR clock and DQS (data strobe) and between DQS and DQ (data). 3. Memory power up 4. Switch from configuration state to access state. It was tested on Pistachio bring up board where DDR was initialized properly and ramstage executed correctly Change-Id: I3bcbce2044327a22fce09b184d85ee11228a6b2b Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: http://review.coreboot.org/10529 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
60 lines
1.7 KiB
Makefile
60 lines
1.7 KiB
Makefile
#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2014 Imagination Technologies
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; version 2 of
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# the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc.
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#
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ifeq ($(CONFIG_CPU_IMGTEC_PISTACHIO),y)
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# We enable CBFS_SPI_WRAPPER for Pistachio targets.
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bootblock-y += clocks.c
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bootblock-y += spi.c
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romstage-y += spi.c
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ramstage-y += spi.c
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ifeq ($(CONFIG_DRIVERS_UART),y)
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bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c
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romstage-y += uart.c
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ramstage-y += uart.c
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endif
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bootblock-y += monotonic_timer.c
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ramstage-y += cbmem.c
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ramstage-y += monotonic_timer.c
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ramstage-y += soc.c
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romstage-y += cbmem.c
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romstage-y += ddr2_init.c
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romstage-y += ddr3_init.c
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romstage-y += romstage.c
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romstage-y += monotonic_timer.c
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CPPFLAGS_common += -Isrc/soc/imgtec/pistachio/include/
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# Generate the actual coreboot bootblock code
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$(objcbfs)/bootblock.raw: $(objcbfs)/bootblock.elf
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@printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
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$(OBJCOPY_bootblock) -O binary $< $@.tmp
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@mv $@.tmp $@
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# Create a complete bootblock which will start up the system
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$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw $(BIMGTOOL)
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@printf " BIMGTOOL $(subst $(obj)/,,$(@))\n"
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$(BIMGTOOL) $< $@ $(call loadaddr,bootblock)
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endif
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