def00be41d
This is a empty struct that has propagated through the superio's & ec's but really does nothing. Time to get rid of it before it adds yet more cruft. However, since this touches many superio's at once we do this in stages by first changing the function type to be a pure procedure. Change-Id: Ibc732e676a9d4f0269114acabc92b15771d27ef2 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5617 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
183 lines
4.7 KiB
C
183 lines
4.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
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* Copyright (C) 2013 Vladimir Serbinenko <phcoder@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <arch/io.h>
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#include <delay.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <device/pci_ids.h>
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#include <arch/io.h>
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#include <ec/lenovo/pmh7/pmh7.h>
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#include <ec/acpi/ec.h>
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#include <ec/lenovo/h8/h8.h>
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#include <northbridge/intel/nehalem/nehalem.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <pc80/mc146818rtc.h>
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#include "dock.h"
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#include "hda_verb.h"
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#include <arch/x86/include/arch/acpigen.h>
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#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
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#include <x86emu/regs.h>
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#include <arch/interrupt.h>
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#endif
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#include <pc80/keyboard.h>
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#include <cpu/x86/lapic.h>
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#include <device/pci.h>
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#include <smbios.h>
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static acpi_cstate_t cst_entries[] = {
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{1, 1, 1000, {0x7f, 1, 2, {0}, 1, 0}},
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{2, 1, 500, {0x01, 8, 0, {0}, DEFAULT_PMBASE + LV2, 0}},
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{2, 17, 250, {0x01, 8, 0, {0}, DEFAULT_PMBASE + LV3, 0}},
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};
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int get_cst_entries(acpi_cstate_t ** entries)
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{
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*entries = cst_entries;
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return ARRAY_SIZE(cst_entries);
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}
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#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
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static int int15_handler(void)
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{
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switch ((X86_EAX & 0xffff)) {
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/* Get boot display. */
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case 0x5f35:
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X86_EAX = 0x5f;
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/* The flags are:
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1 - VGA
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4 - DisplayPort
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8 - LCD
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*/
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X86_ECX = 0x8;
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return 1;
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case 0x5f40:
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X86_EAX = 0x5f;
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X86_ECX = 0x2;
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return 1;
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default:
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printk(BIOS_WARNING, "Unknown INT15 function %04x!\n",
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X86_EAX & 0xffff);
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return 0;
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}
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}
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#endif
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const char *smbios_mainboard_version(void)
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{
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return "Lenovo X201";
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}
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/* Audio Setup */
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extern const u32 *cim_verb_data;
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extern u32 cim_verb_data_size;
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static void verb_setup(void)
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{
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cim_verb_data = mainboard_cim_verb_data;
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cim_verb_data_size = sizeof(mainboard_cim_verb_data);
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}
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static void mainboard_init(device_t dev)
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{
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printk(BIOS_SPEW, "starting SPI configuration\n");
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/* Configure SPI. */
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RCBA32(0x3800) = 0x07ff0500;
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RCBA32(0x3804) = 0x3f046008;
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RCBA32(0x3808) = 0x0058efc0;
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RCBA32(0x384c) = 0x92000000;
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RCBA32(0x3850) = 0x00000a0b;
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RCBA32(0x3858) = 0x07ff0500;
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RCBA32(0x385c) = 0x04ff0003;
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RCBA32(0x3860) = 0x00020001;
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RCBA32(0x3864) = 0x00000fff;
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RCBA32(0x3874) = 0;
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RCBA32(0x3890) = 0xf8400000;
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RCBA32(0x3894) = 0x143b5006;
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RCBA32(0x3898) = 0x05200302;
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RCBA32(0x389c) = 0x0601209f;
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RCBA32(0x38b0) = 0x00000004;
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RCBA32(0x38b4) = 0x03040002;
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RCBA32(0x38c0) = 0x00000007;
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RCBA32(0x38c4) = 0x00802005;
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RCBA32(0x38c8) = 0x00002005;
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RCBA32(0x3804) = 0x3f04e008;
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printk(BIOS_SPEW, "SPI configured\n");
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/* This sneaked in here, because X201 SuperIO chip isn't really
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connected to anything and hence we don't init it.
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*/
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pc_keyboard_init();
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/* Enable expresscard hotplug events. */
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pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 3)),
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0xd8,
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pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 3)), 0xd8)
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| (1 << 30));
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pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x1c, 3)),
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0x42, 0x142);
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}
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static void mainboard_enable(device_t dev)
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{
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device_t dev0;
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u16 pmbase;
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dev->ops->init = mainboard_init;
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pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
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PMBASE) & 0xff80;
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printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase);
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outl(0, pmbase + SMI_EN);
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enable_lapic();
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pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_BASE,
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DEFAULT_GPIOBASE | 1);
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pci_write_config8(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_CNTL,
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0x10);
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/* If we're resuming from suspend, blink suspend LED */
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dev0 = dev_find_slot(0, PCI_DEVFN(0, 0));
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if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC)
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ec_write(0x0c, 0xc7);
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#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
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/* Install custom int15 handler for VGA OPROM */
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mainboard_interrupt_handlers(0x15, &int15_handler);
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#endif
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verb_setup();
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}
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struct chip_operations mainboard_ops = {
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.enable_dev = mainboard_enable,
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};
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