63f8c0af4b
The THERMTRIP status bit is in GBLRST_CAUSE instead of GEN_PMCON like the EDSv1 indicates. Read this status bit and add an elog event if THERMTRIP has fired. BUG=chrome-os-partner:48438 BRANCH=none TEST=tested on chell EVT after thermtrip fired Change-Id: Icd52b753c7f3ab0d48095279f1255dd2dd08fd59 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b090c7897a8f99a685f523990235d83fafa063b2 Original-Change-Id: I5a287d7fdae2ba8ae8585cb9a4d4dd873393e1e6 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/317242 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12980 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
124 lines
3.4 KiB
C
124 lines
3.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <bootstate.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <stdint.h>
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#include <elog.h>
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#include <soc/pm.h>
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#include <soc/pmc.h>
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static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start)
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{
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int i;
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gpe0_sts &= gpe0_en;
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for (i = 0; i <= 31; i++) {
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if (gpe0_sts & (1 << i))
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elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start);
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}
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}
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static void pch_log_wake_source(struct chipset_power_state *ps)
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{
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/* Power Button */
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if (ps->pm1_sts & PWRBTN_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0);
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/* RTC */
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if (ps->pm1_sts & RTC_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0);
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/* PCI Express (TODO: determine wake device) */
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if (ps->pm1_sts & PCIEXPWAK_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0);
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/* PME (TODO: determine wake device) */
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if (ps->gpe0_sts[GPE_STD] & PME_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0);
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/* Internal PME (TODO: determine wake device) */
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if (ps->gpe0_sts[GPE_STD] & PME_B0_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0);
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/* SMBUS Wake */
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if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0);
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/* Log GPIO events in set 1-3 */
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pch_log_gpio_gpe(ps->gpe0_sts[GPE_31_0], ps->gpe0_en[GPE_31_0], 0);
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pch_log_gpio_gpe(ps->gpe0_sts[GPE_63_32], ps->gpe0_en[GPE_63_32], 32);
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pch_log_gpio_gpe(ps->gpe0_sts[GPE_95_64], ps->gpe0_en[GPE_95_64], 64);
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/* Treat the STD as an extension of GPIO to obtain visibility. */
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pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96);
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}
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static void pch_log_power_and_resets(struct chipset_power_state *ps)
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{
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/* Thermal Trip */
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if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP)
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elog_add_event(ELOG_TYPE_THERM_TRIP);
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/* PWR_FLR Power Failure */
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if (ps->gen_pmcon_b & PWR_FLR)
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elog_add_event(ELOG_TYPE_POWER_FAIL);
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/* SUS Well Power Failure */
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if (ps->gen_pmcon_b & SUS_PWR_FLR)
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elog_add_event(ELOG_TYPE_SUS_POWER_FAIL);
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/* TCO Timeout */
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if (ps->prev_sleep_state != 3 &&
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ps->tco2_sts & TCO2_STS_SECOND_TO)
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elog_add_event(ELOG_TYPE_TCO_RESET);
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/* Power Button Override */
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if (ps->pm1_sts & PRBTNOR_STS)
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elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE);
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/* RTC reset */
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if (ps->gen_pmcon_b & RTC_BATTERY_DEAD)
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elog_add_event(ELOG_TYPE_RTC_RESET);
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/* Host Reset Status */
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if (ps->gen_pmcon_b & HOST_RST_STS)
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elog_add_event(ELOG_TYPE_SYSTEM_RESET);
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/* ACPI Wake Event */
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if (ps->prev_sleep_state != SLEEP_STATE_S0)
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elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state);
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}
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static void pch_log_state(void *unused)
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{
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struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
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if (ps == NULL) {
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printk(BIOS_ERR,
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"Not logging power state information. Power state not found in cbmem.\n");
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return;
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}
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/* Power and Reset */
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pch_log_power_and_resets(ps);
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/* Wake Sources */
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pch_log_wake_source(ps);
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}
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BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, pch_log_state, NULL);
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