9b1f3cc6fb
This patch pulls control of the memory pool serving allocations from the CBFS_CACHE memlayout area into cbfs.c and makes it a core part of the CBFS API. Previously, platforms would independently instantiate this as part of boot_device_ro() (mostly through cbfs_spi.c). The new cbfs_cache pool is exported as a global so these platforms can still use it to directly back rdev_mmap() on their boot device, but the cbfs_cache can now also use it to directly make allocations itself. This is used to allow transparent decompression support in cbfs_map(). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I0d52b6a8f582a81a19fd0fd663bb89eab55a49d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
120 lines
2.7 KiB
C
120 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* This file provides a common CBFS wrapper for SPI storage. SPI driver
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* context is expanded with the buffer descriptor used to store data read from
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* SPI.
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*/
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#include <boot_device.h>
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#include <cbfs.h>
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#include <console/console.h>
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#include <spi_flash.h>
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#include <symbols.h>
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#include <cbmem.h>
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#include <stdint.h>
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#include <timer.h>
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static struct spi_flash spi_flash_info;
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static bool spi_flash_init_done;
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/*
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* SPI speed logging for big transfers available with BIOS_DEBUG. The format is:
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*
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* read SPI 0x62854 0x7db7: 10416 us, 3089 KB/s, 24.712 Mbps
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*
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* The important number is the last one. It should roughly match your SPI
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* clock. If it doesn't, your driver might need a little tuning.
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*/
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static ssize_t spi_readat(const struct region_device *rd, void *b,
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size_t offset, size_t size)
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{
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struct stopwatch sw;
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bool show = size >= 4 * KiB && console_log_level(BIOS_DEBUG);
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if (show)
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stopwatch_init(&sw);
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if (spi_flash_read(&spi_flash_info, offset, size, b))
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return -1;
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if (show) {
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long usecs;
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usecs = stopwatch_duration_usecs(&sw);
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u64 speed; /* KiB/s */
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int bps; /* Bits per second */
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speed = size * (u64)1000 / usecs;
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bps = speed * 8;
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printk(BIOS_DEBUG, "read SPI %#zx %#zx: %ld us, %lld KB/s, %d.%03d Mbps\n",
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offset, size, usecs, speed, bps / 1000, bps % 1000);
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}
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return size;
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}
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static ssize_t spi_writeat(const struct region_device *rd, const void *b,
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size_t offset, size_t size)
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{
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if (spi_flash_write(&spi_flash_info, offset, size, b))
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return -1;
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return size;
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}
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static ssize_t spi_eraseat(const struct region_device *rd,
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size_t offset, size_t size)
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{
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if (spi_flash_erase(&spi_flash_info, offset, size))
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return -1;
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return size;
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}
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/* Provide all operations on the same device. */
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static const struct region_device_ops spi_ops = {
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.mmap = mmap_helper_rdev_mmap,
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.munmap = mmap_helper_rdev_munmap,
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.readat = spi_readat,
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.writeat = spi_writeat,
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.eraseat = spi_eraseat,
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};
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static struct mmap_helper_region_device mdev =
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MMAP_HELPER_DEV_INIT(&spi_ops, 0, CONFIG_ROM_SIZE, &cbfs_cache);
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void boot_device_init(void)
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{
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int bus = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS;
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int cs = 0;
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if (spi_flash_init_done == true)
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return;
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if (spi_flash_probe(bus, cs, &spi_flash_info))
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return;
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spi_flash_init_done = true;
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}
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/* Return the CBFS boot device. */
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const struct region_device *boot_device_ro(void)
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{
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if (spi_flash_init_done != true)
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return NULL;
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return &mdev.rdev;
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}
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/* The read-only and read-write implementations are symmetric. */
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const struct region_device *boot_device_rw(void)
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{
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return boot_device_ro();
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}
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const struct spi_flash *boot_device_spi_flash(void)
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{
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boot_device_init();
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if (spi_flash_init_done != true)
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return NULL;
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return &spi_flash_info;
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}
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