e07e13d7fd
This updates FSP UPD headers that adds new fields. Importantly there are new FSPS UPD fields that allow to specify some BARs. They are needed by FSP SiliconInit API to work properly. Change-Id: Ie268c57c66b4d8fd6e00835916004058ff05762e Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14217 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
120 lines
3.5 KiB
C
120 lines
3.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Intel Corp.
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* (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
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* (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <bootstate.h>
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#include <console/console.h>
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#include <cpu/cpu.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <fsp/api.h>
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#include <fsp/util.h>
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#include <memrange.h>
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#include <soc/iomap.h>
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#include <soc/cpu.h>
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#include <soc/pci_devs.h>
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#include "chip.h"
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static void pci_domain_set_resources(device_t dev)
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{
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assign_resources(dev->link_list);
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}
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static struct device_operations pci_domain_ops = {
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.read_resources = pci_domain_read_resources,
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.set_resources = pci_domain_set_resources,
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.enable_resources = NULL,
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.init = NULL,
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.scan_bus = pci_domain_scan_bus,
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.ops_pci_bus = pci_bus_default_ops,
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};
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static struct device_operations cpu_bus_ops = {
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.read_resources = DEVICE_NOOP,
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.set_resources = DEVICE_NOOP,
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.enable_resources = DEVICE_NOOP,
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.init = apollolake_init_cpus,
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.scan_bus = NULL,
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};
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static void enable_dev(device_t dev)
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{
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/* Set the operations if it is a special bus type */
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if (dev->path.type == DEVICE_PATH_DOMAIN) {
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dev->ops = &pci_domain_ops;
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} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
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dev->ops = &cpu_bus_ops;
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}
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}
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static void soc_init(void *data)
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{
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struct range_entry range;
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/* TODO: tigten this resource range */
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/* TODO: fix for S3 resume, as this would corrupt OS memory */
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range_entry_init(&range, 0x200000, 4ULL*GiB, 0);
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fsp_silicon_init(&range);
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}
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void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
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{
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struct FSP_S_CONFIG *silconfig = &silupd->FspsConfig;
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static struct soc_intel_apollolake_config *cfg;
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/* Load VBT before devicetree-specific config. */
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silconfig->GraphicsConfigPtr = fsp_load_vbt();
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struct device *dev = NB_DEV_ROOT;
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if (!dev && !dev->chip_info) {
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printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
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return;
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}
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cfg = dev->chip_info;
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silconfig->PcieRpClkReqNumber[0] = cfg->pcie_rp0_clkreq_pin;
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silconfig->PcieRpClkReqNumber[1] = cfg->pcie_rp1_clkreq_pin;
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silconfig->PcieRpClkReqNumber[2] = cfg->pcie_rp2_clkreq_pin;
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silconfig->PcieRpClkReqNumber[3] = cfg->pcie_rp3_clkreq_pin;
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silconfig->PcieRpClkReqNumber[4] = cfg->pcie_rp4_clkreq_pin;
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silconfig->PcieRpClkReqNumber[5] = cfg->pcie_rp5_clkreq_pin;
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/* Our defaults may not match FSP defaults, so set them explicitly */
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silconfig->AcpiBase = ACPI_PMIO_BASE;
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/* First 4k in BAR0 is used for IPC, real registers start at 4k offset */
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silconfig->PmcBase = PMC_BAR0 + 0x1000;
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silconfig->P2sbBase = P2SB_BAR;
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}
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struct chip_operations soc_intel_apollolake_ops = {
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CHIP_NAME("Intel Apollolake SOC")
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.enable_dev = &enable_dev,
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.init = &soc_init
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};
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static void fsp_notify_dummy(void *arg)
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{
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enum fsp_notify_phase ph = (enum fsp_notify_phase) arg;
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if (fsp_notify(ph) != FSP_SUCCESS)
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printk(BIOS_CRIT, "FspNotify failed!\n");
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}
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BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, fsp_notify_dummy,
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(void *) AFTER_PCI_ENUM);
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BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, fsp_notify_dummy,
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(void *) READY_TO_BOOT);
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BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, fsp_notify_dummy,
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(void *) READY_TO_BOOT);
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