e1c36aecd8
In RS485 mode RTS line acts as a transceiver direction control. The datasheet is not very clear about the polarity but register setting here is tested to drive nRTS line high when transmitting. Also note revision of B of the super-IO has errata and 8N1 setting does not work properly, you would need revision C of the chip assembled to fix this. Change-Id: I705fe0c5a5f8369b0a9358a64c74500238b5c4ba Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14998 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> |
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|---|---|---|
| .. | ||
| acpi | ||
| acpi_tables.c | ||
| BiosCallOuts.c | ||
| board_info.txt | ||
| buildOpts.c | ||
| cmos.default | ||
| cmos.layout | ||
| devicetree.cb | ||
| dsdt.asl | ||
| gpio_ftns.c | ||
| gpio_ftns.h | ||
| HYNIX-H5TQ2G83CFR.spd.hex | ||
| HYNIX-H5TQ4G83MFR.spd.hex | ||
| irq_tables.c | ||
| Kconfig | ||
| Kconfig.name | ||
| mainboard.c | ||
| Makefile.inc | ||
| mptable.c | ||
| OemCustomize.c | ||
| OptionsIds.h | ||
| platform_cfg.h | ||
| PlatformGnbPcieComplex.h | ||
| romstage.c | ||