60a4643d6f
The SMU mailbox access code from Picasso can be reused in the next generation, so factor out the code to soc/amd/common/block/smu. Since the mailbox register offsets in the indirect address space, the number of arguments and the message IDs don't always match between different devices, keep those in the soc-specific directories. Change-Id: Ibaf5b91ab35428e4c771e7163c6e0c4fc50371e7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
17 lines
490 B
C
17 lines
490 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <amdblocks/smu.h>
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#include <soc/smu.h>
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/*
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* Request the SMU to put system into S3, S4, or S5. On entry, SlpTyp determines S-State and
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* SlpTypeEn gets set by the SMU. Function does not return if successful.
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*/
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void smu_sx_entry(void)
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{
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struct smu_payload msg = { 0 }; /* Unused for SMC_MSG_S3ENTRY */
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printk(BIOS_DEBUG, "SMU: Put system into S3/S4/S5\n");
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send_smu_message(SMC_MSG_S3ENTRY, &msg);
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}
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