e26c4a4611
Cannon lake PCH-H is added to support coffee lake RVP11 and coffee lake RVP8 platforms. - Add new device IDs for LPC, PCIE, PMC, I2C, UART, SMBUS, XHCI, P2SB, SRAM, AUDIO, CSE0, XDCI, SD, MCH and graphics device. - Add new device IDs to intel common code respectively. - Add CPU, LPC, GD, MCH entry to report_platform.c to identify RVP11 & RVP8. - CNL PCH-H supports 24 pcie root ports and 4 I2C controllers, hence chip.c is modified accordingly. - Add board type UserBd UPD to BOARD_TYPE_DESKTOP for both RVP11 & RVP8. BUG=None TEST=successfully boot both CFL RVP11 & RVP8, verified all the enabled devices are enumerated and cross checked devices ids in serial logs and UEFI shell. Change-Id: I4b6af88d467382250aecb4102878b1c5af92ccd4 Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/28718 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> |
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.. | ||
dram | ||
azalia.h | ||
azalia_device.h | ||
cardbus.h | ||
device.h | ||
drm_dp_helper.h | ||
early_smbus.h | ||
hypertransport.h | ||
hypertransport_def.h | ||
i2c.h | ||
i2c_bus.h | ||
i2c_simple.h | ||
path.h | ||
pci.h | ||
pci_def.h | ||
pci_ehci.h | ||
pci_ids.h | ||
pci_ops.h | ||
pci_rom.h | ||
pciexp.h | ||
pcix.h | ||
pnp.h | ||
pnp_def.h | ||
resource.h | ||
smbus.h | ||
smbus_def.h | ||
spi.h |