69486cac74
Move the stoneyridge AcpiMmio code into soc/amd/common. The SB800 southbridge introduced the MMIO hardware blocks at 0xfed80000 commonly known as AcpiMmio. Implementations beginning with Mullins enable decode in PMx04. Older designs use PMx24 and allow for configuring the base address. Future work may support the older version. Comparing the documentation for AMD's RRGs and BKDGs, it is evident that the block locations have not been reassigned across products. In some cases, address locations are deprecated and new ones consumed, e.g. the early GPIO blocks were simpler at offset 0x100 and the newer GPIO banks are now at 0x1500, 0x1600, and 0x1700. Note: Do not infer the definitions within the hardware blocks are consistent across family/model products. BUG=b:131682806 Change-Id: I083b6339cd29e72289e63c9331a815c46d71600d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32649 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
73 lines
1.8 KiB
C
73 lines
1.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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* Copyright (C) 2017 Google, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <reset.h>
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#include <soc/northbridge.h>
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#include <soc/pci_devs.h>
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#include <device/pci_ops.h>
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#include <soc/southbridge.h>
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#include <amdblocks/acpimmio.h>
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#include <amdblocks/reset.h>
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void set_warm_reset_flag(void)
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{
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u32 htic;
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htic = pci_read_config32(SOC_HT_DEV, HT_INIT_CONTROL);
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htic |= HTIC_COLD_RST_DET;
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pci_write_config32(SOC_HT_DEV, HT_INIT_CONTROL, htic);
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}
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int is_warm_reset(void)
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{
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u32 htic;
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htic = pci_read_config32(SOC_HT_DEV, HT_INIT_CONTROL);
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return !!(htic & HTIC_COLD_RST_DET);
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}
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/* Clear bits 5, 9 & 10, used to signal the reset type */
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static void clear_bios_reset(void)
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{
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u32 htic;
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htic = pci_read_config32(SOC_HT_DEV, HT_INIT_CONTROL);
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htic &= ~HTIC_BIOSR_DETECT;
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pci_write_config32(SOC_HT_DEV, HT_INIT_CONTROL, htic);
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}
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void do_cold_reset(void)
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{
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clear_bios_reset();
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/* De-assert and then assert all PwrGood signals on CF9 reset. */
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pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) |
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TOGGLE_ALL_PWR_GOOD);
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outb(RST_CMD | SYS_RST, SYS_RESET);
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}
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void do_warm_reset(void)
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{
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set_warm_reset_flag();
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clear_bios_reset();
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/* Assert reset signals only. */
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outb(RST_CMD | SYS_RST, SYS_RESET);
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}
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void do_board_reset(void)
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{
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/* TODO: Would a warm_reset() suffice? */
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do_cold_reset();
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}
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