69486cac74
Move the stoneyridge AcpiMmio code into soc/amd/common. The SB800 southbridge introduced the MMIO hardware blocks at 0xfed80000 commonly known as AcpiMmio. Implementations beginning with Mullins enable decode in PMx04. Older designs use PMx24 and allow for configuring the base address. Future work may support the older version. Comparing the documentation for AMD's RRGs and BKDGs, it is evident that the block locations have not been reassigned across products. In some cases, address locations are deprecated and new ones consumed, e.g. the early GPIO blocks were simpler at offset 0x100 and the newer GPIO banks are now at 0x1500, 0x1600, and 0x1700. Note: Do not infer the definitions within the hardware blocks are consistent across family/model products. BUG=b:131682806 Change-Id: I083b6339cd29e72289e63c9331a815c46d71600d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32649 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
38 lines
1.1 KiB
C
38 lines
1.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* Utilities for SMM setup
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*/
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#include <console/console.h>
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#include <amdblocks/acpimmio.h>
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#include <soc/southbridge.h>
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#include <soc/smi.h>
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void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
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{
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printk(BIOS_DEBUG, "%s STUB!!!\n", __func__);
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}
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/** Set the EOS bit and enable SMI generation from southbridge */
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void enable_smi_generation(void)
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{
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uint32_t reg = smi_read32(SMI_REG_SMITRIG0);
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reg &= ~SMITRG0_SMIENB; /* Enable SMI generation */
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reg |= SMITRG0_EOS; /* Set EOS bit */
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smi_write32(SMI_REG_SMITRIG0, reg);
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}
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