faf7a8e859
The Harcuvar CRB is a reference platform of Intel Atom C3000 SoC
("Denverton" and "Denverton-NS") for the communications segment/market.
The MohonPeak coreboot was used as the starting template with
additions/modifications from other Intel Apollo Lake/Skylake coreboot.
Tested with TianoCore payload (UDK2015) and Poky (Yocto
Project Reference Distro) 2.0 with kernel 4.1.8 booted from
SATA drive and external USB pendrive.
Change-Id: I088833e36e2d22d1fe1610b8dca1454092da511a
Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com>
Reviewed-on: https://review.coreboot.org/20862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
49 lines
1.2 KiB
Text
49 lines
1.2 KiB
Text
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2014 - 2017 Intel Corporation.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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if BOARD_INTEL_HARCUVAR
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select SOC_INTEL_DENVERTON_NS
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select BOARD_ROMSIZE_KB_16384
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select HAVE_ACPI_TABLES
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config MAINBOARD_DIR
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string
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default intel/harcuvar
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config MAINBOARD_PART_NUMBER
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string
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default "Harcuvar CRB"
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config MAINBOARD_VENDOR
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string
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default "Intel"
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config ENABLE_FSP_MEMORY_DOWN
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bool "Enable Memory Down"
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default n
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help
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Select this option to enable Memory Down function.
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config SPD_LOC
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depends on ENABLE_FSP_MEMORY_DOWN
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hex "SPD binary location in cbfs"
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default 0xfffdf000
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help
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Location of SPD binary for memory down function.
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endif # BOARD_INTEL_HARCUVAR
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