e4ac9c043a
wwan_enable was never used. wlan_enable isn't something for device tree but for CMOS config if at all. Change-Id: I765d9d6f0b73b7dc5a57c0c630a53b4b7a0b48cb Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4651 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
144 lines
3.8 KiB
Text
144 lines
3.8 KiB
Text
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2009 coresystems GmbH
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## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
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##
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## This program is free software; you can redistribute it and/or
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## modify it under the terms of the GNU General Public License as
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## published by the Free Software Foundation; version 2 of
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## the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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## MA 02110-1301 USA
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##
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chip northbridge/intel/nehalem
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# Enable DisplayPort Hotplug with 6ms pulse
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register "gpu_dp_d_hotplug" = "0x06"
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# Enable Panel as LVDS and configure power delays
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register "gpu_panel_port_select" = "0" # LVDS
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register "gpu_panel_power_cycle_delay" = "3"
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register "gpu_panel_power_up_delay" = "250"
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register "gpu_panel_power_down_delay" = "250"
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register "gpu_panel_power_backlight_on_delay" = "2500"
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register "gpu_panel_power_backlight_off_delay" = "2500"
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register "gpu_cpu_backlight" = "0x58d"
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register "gpu_pch_backlight" = "0x061a061a"
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chip ec/lenovo/pmh7
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device pnp ff.1 on # dummy
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end
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register "backlight_enable" = "0x01"
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register "dock_event_enable" = "0x01"
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end
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chip ec/lenovo/h8
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device pnp ff.2 on # dummy
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io 0x60 = 0x62
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io 0x62 = 0x66
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io 0x64 = 0x1600
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io 0x66 = 0x1604
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end
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register "config0" = "0xa6"
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register "config1" = "0x05"
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register "config2" = "0xa0"
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register "config3" = "0x01"
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register "beepmask0" = "0xfe"
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register "beepmask1" = "0x96"
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register "event2_enable" = "0xff"
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register "event3_enable" = "0xff"
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register "event4_enable" = "0xf4"
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register "event5_enable" = "0x3c"
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register "event6_enable" = "0x80"
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register "event7_enable" = "0x01"
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register "eventc_enable" = "0x3c"
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register "event8_enable" = "0x01"
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register "event9_enable" = "0xff"
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register "eventa_enable" = "0xff"
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register "eventb_enable" = "0xff"
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register "eventc_enable" = "0xff"
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register "eventd_enable" = "0xff"
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register "trackpoint_enable" = "0x03"
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end
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device cpu_cluster 0 on
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chip cpu/intel/model_206ax
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device lapic 0 on end
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end
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end
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device domain 0 on
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device pci 00.0 on # Host bridge
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subsystemid 0x17aa 0x2193
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end
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device pci 02.0 on # VGA controller
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subsystemid 0x17aa 0x215a
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end
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chip southbridge/intel/ibexpeak
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register "pirqa_routing" = "0x0b"
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register "pirqb_routing" = "0x0b"
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register "pirqc_routing" = "0x0b"
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register "pirqd_routing" = "0x0b"
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register "pirqe_routing" = "0x0b"
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register "pirqf_routing" = "0x0b"
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register "pirqg_routing" = "0x0b"
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register "pirqh_routing" = "0x0b"
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# GPI routing
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# 0 No effect (default)
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# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
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# 2 SCI (if corresponding GPIO_EN bit is also set)
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register "gpi1_routing" = "2"
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register "gpi13_routing" = "2"
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register "sata_ahci" = "0x1"
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register "sata_port_map" = "0x33"
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register "gpe0_en" = "0x20022046"
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register "alt_gp_smi_en" = "0x0000"
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device pci 16.2 on # IDE/SATA
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subsystemid 0x17aa 0x2161
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end
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device pci 19.0 on # Ethernet
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subsystemid 0x17aa 0x2153
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end
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device pci 1a.0 on # USB2 EHCI
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subsystemid 0x17aa 0x2163
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end
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device pci 1b.0 on # Audio Controller
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subsystemid 0x17aa 0x215e
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end
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device pci 1d.0 on # USB2 EHCI
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subsystemid 0x17aa 0x2163
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end
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device pci 1f.0 on # PCI-LPC bridge
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subsystemid 0x17aa 0x2166
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end
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device pci 1f.2 on # IDE/SATA
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subsystemid 0x17aa 0x2168
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end
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device pci 1f.3 on # SMBUS
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subsystemid 0x17aa 0x2167
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end
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end
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end
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end
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