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Michael Niewöhner e4c784bd0d soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default 
There are boards that do not need a specific domain_vr_config because
the defaults provided by the soc code are sufficient. Currently, this
means that these boards can't benefit from lower power states (PSI 3
and 4) because the settings default to being disabled since at the time
the defaults have been defined (2015) there were bugs in FSP in this
regard.

Set the default values of psiXenable to 1 for boards that do not have a
domain_vr_config setting in their devicetree, just like Cannon Lake
does.

Boards that have a domain_vr_config and set their specific settings are
not affected at all. Currently, there are only three boards that have
no domain_vr_config:

- supermicro/x11-lga1151-series
  These boards have a MPS MP2955 which we can assume support for PS3
  (the MP2965 and MP2935 support it, too).
  S-series CPUs with a 1151 socket do not have C9/C10 but only C8 and
  since only C10 makes use of PS4, those CPUs won't ever request PS4.
  That means we do not need to disable it explicitly for these boards.

- 51nb/x210:
  Needs testing and/or VR datasheet check for PS3/PS4 support

Change-Id: I5b5fd9fb3b9b89e80c47f15d706e2dd62dcc0748
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39980
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-03 16:23:01 +00:00
3rdparty 3rdparty/libgfxinit: Update submodule pointer 2020-03-09 08:20:12 +00:00
configs configs: Add builder config to create a working Cedar Island CRB 2020-03-26 18:15:04 +00:00
Documentation Doc/mb/index.md: Fix mainboard vendor order 2020-04-03 13:43:35 +00:00
LICENSES LICENSES: Add licenses used in the coreboot repo 2019-10-30 08:23:51 +00:00
payloads cros_ec: add chrome EC headers to include path 2020-04-01 09:19:48 +00:00
src soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default 2020-04-03 16:23:01 +00:00
util util/sconfig: emit NULL sibling fields 2020-03-30 08:37:56 +00:00
.checkpatch.conf
.clang-format lint/clang-format: set to 96 chars per line 2019-06-13 20:14:00 +00:00
.editorconfig Add .editorconfig file 2019-09-10 12:52:18 +00:00
.gitignore cbfstool: Build vboot library 2020-03-23 08:34:23 +00:00
.gitmodules submodules: Add 3rdparty/amd_blobs 2019-10-31 12:28:38 +00:00
.gitreview
AUTHORS AUTHORS: Add authors from util/ 2020-03-18 18:22:37 +00:00
COPYING
gnat.adc
MAINTAINERS Remove myself from MAINTAINERS file 2020-04-01 09:03:18 +00:00
Makefile cbfstool: Build vboot library 2020-03-23 08:34:23 +00:00
Makefile.inc Makefile.inc: Don't run ifittool with CONFIG_UPDATE_IMAGE 2020-03-25 10:51:50 +00:00
README.md README.md: Remove link to deprecated wiki 2019-11-16 20:39:55 +00:00
toolchain.inc Makefile: Remove romcc 2019-12-27 08:59:59 +00:00

README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.